Will this open drain LED driver circuit work ?
The open drain IO is governed by the following equation
0.5 <= V_LED_OUT <= 3.6 V (abs_max)
V_LED_OUT is the voltage from open drain IO pin to ground.
The FPGA is iCE40 Ultra.
LED driver Tech-note. This tech-note provides the governing equations in Appendix-C.
CDBU0520 is a schottky diode with a VF = 0.36 (max) at a IF = 100 mA.
SFT722N-S is the LED with VF= 3.2V (typical) at IF = 20 mA.
When the IO is switched on it can sink upto 24 mA (max). In the ON state of the IO , the voltage at the fpga pin will be (5 - 3.2 - 0.47 - R_drop). It would always be less than 3.2 in the ON state of the driver. So the above equation is satisfied and there won't be harm to the IO. In this case , what is the current that will be drawn from the supply ? since diode and LED forward currents are different.
Now , when the IO is tristated , i think the equation would fail. since both the LED and diode would be reverse biased and more than 3.6 V would be available at the IO and it could get damaged. Is this analysis correct ?
When the open drain IO is tristated , what is the voltage at the pin , how to calculate it for the current scenario ?
Is there any option to get this circuit to satisfy the above equation even in the off state ?
I fundamentally want to understand the circuit operation when IO is tri-stated(OFF). How will the voltage at IO will be less than 3.6(abs_max) ? If the leakage of diode and LED and IO_buffer determine the voltage at IO pin could you provide elaboration with example either general or specific to this circuit.