# Designing a open drain LED driver

Will this open drain LED driver circuit work ?

The open drain IO is governed by the following equation
0.5 <= V_LED_OUT <= 3.6 V (abs_max)
V_LED_OUT is the voltage from open drain IO pin to ground.
The FPGA is iCE40 Ultra.
LED driver Tech-note. This tech-note provides the governing equations in Appendix-C.
CDBU0520 is a schottky diode with a VF = 0.36 (max) at a IF = 100 mA.
SFT722N-S is the LED with VF= 3.2V (typical) at IF = 20 mA.

When the IO is switched on it can sink upto 24 mA (max). In the ON state of the IO , the voltage at the fpga pin will be (5 - 3.2 - 0.47 - R_drop). It would always be less than 3.2 in the ON state of the driver. So the above equation is satisfied and there won't be harm to the IO. In this case , what is the current that will be drawn from the supply ? since diode and LED forward currents are different.

Now , when the IO is tristated , i think the equation would fail. since both the LED and diode would be reverse biased and more than 3.6 V would be available at the IO and it could get damaged. Is this analysis correct ?

When the open drain IO is tristated , what is the voltage at the pin , how to calculate it for the current scenario ?

Is there any option to get this circuit to satisfy the above equation even in the off state ?

I fundamentally want to understand the circuit operation when IO is tri-stated(OFF). How will the voltage at IO will be less than 3.6(abs_max) ? If the leakage of diode and LED and IO_buffer determine the voltage at IO pin could you provide elaboration with example either general or specific to this circuit.

• Got a datasheet for whatever that "open drain IO" is? – uint128_t May 7 '16 at 16:42
• In the off state, the voltage at the open drain IO is determined by the balance of the leakage current of the IO pin and the diodes. There is not enough device data to make a calculation. But it is safe to say that with your configuration the leakage current will be very low and the IO pin would work fine even not knowing the exact voltage at off state. – rioraxe May 7 '16 at 20:22
• @rioraxe , could you elaborate more on this. I have added the fpga datasheet to problem description. If i only consider the LED in the circuit , taking its leakage as 1 uA at VR = 10V and say the IO leakage is 10 uA , then what is the voltage at the IO pin ? When you say the voltage at the IO pin will depend on the balance of IO pin leakage and diode leakage , could you provide a general example for this if the information provided is not enough. – user22348 May 8 '16 at 4:10
• The problem is not the current but the voltage. Anyway, the datasheet shows that no component except the LED itself is needed. – CL. May 8 '16 at 5:25
• @CL , There won't be any issue to directly drive the LED when vdd for LED is same as vccio. But if you use 5v or higher vdd then the abs max at the io is a concern. – user22348 May 8 '16 at 6:20

The voltage drop is easy to calculate for the resistor: U = R * I, and with a current of zero, the voltage drop is zero, too. In general, Ohm's Law cannot be applied this way to diodes, but for the special case of zero current, they behave the same: they do not drop any voltage. So when the output is off, the voltage at the I/O pin is 5 V.

The datasheet says:

There are three outputs on each device that can sink up to 24 mA current. These outputs are open-drain outputs, and provides sinking current to an LED connecting to the positive supply.

Here, "positive supply" means the I/O driver supply voltage, which must not be higher than 3.6 V. This is confirmed by the absolute maximum rating for the applied voltage to a tri-stated I/O, which is also 3.6 V.

To avoid exceeding this voltage, you can put a buffering transistor between the output and the LED; when that transistor is off, the LED is disconnected from the FPGA, and the transistor is capable of withstanding the 5 V:

(Due to the inverting action of the transistor, this requires a push-pull output. The BJT could be replaced with a FET.)

However, all of this is actually not necessary. The datasheet also says:

The embedded RGB PWM IP, with the three 24 mA constant current RGB outputs on the iCE40 Ultra provides all the necessary logic to directly drive the service LED, without the need of external MOSFET or buffer.

So you do not need a resistor to limit the current; the output already can do it.

Just connect the LED directly to the output, and to the FPGA's I/O supply (3.3 V), and configure the output to supply the appropriate amount of current for the LED (it probably needs only 12 mA or less to be bright enough).

• Just because a diode isn't ohmic doesn't mean it doesn't obey Ohms' law. For example, a white LED with 3.5 volts across it and 20 milliamps through it must exhibit a resistance of $$R = \frac{E}{I} = \frac{3.5V}{0.02A} = 175\Omega$$ at that point. – EM Fields May 7 '16 at 17:55
• @EMFields A diode does not have a fixed R, so it is not possible to compute the voltage drop this way. – CL. May 7 '16 at 18:12
• Take a closer look at what I wrote and you might notice that I wasn't computing the voltage drop across the diode, which is one of its intrinsic properties, I was calculating its resistance at a particular point on its EI curve. Surely you must understand that if anything allows charge to flow when the pressure of voltage is impressed across it, its resistance will determine the magnitude of the current, yes? – EM Fields May 7 '16 at 18:25

Your circuit will work, but can be simplified.

You don't need the schottky diode.

When the IO is on, the max. current that could flow (assuming the driver RDSON is negligible) is (5V-VLED)/R1. If VLED is 3.2 V, and 100 ohm, this is 18 mA which is OK. Even if the '5 V' is within typical tolerances (say 5 %), you'll be OK.

When the driver turns off, the current will stop, and the LED voltage will become zero.

• This does not answer the question (value of V_LED_OUT). – CL. May 7 '16 at 18:14
• This answer also doesn't address the issue that the open drain transistor in OP's drawing is the output of a microcontroller that likely has esd protection that won't let its output be pulled up to 5 V. – The Photon May 7 '16 at 18:24
• As rioaxe wrote above, the leakage current in the LED when the IO driver is off will be very small if the IO voltage is 3.6 V (leaving < 1.4 V across the LED), and won't harm the IO. Worst case there could be a uA or so in the LED -- won't cause any harm. Even that can be eliminated with 1 Mohm in parallel with the LED. OP didn't give enough information to allow a more sophisticated solution. – jp314 May 8 '16 at 2:49
• @jp314 , I added the fpga datasheet link to the problem description. Please let me know what other information may be needed. – user22348 May 8 '16 at 4:04
• Datasheet says I/O voltage is 3.46 max operating (while absolute max is 3.6, you should not operate at that level for long term reliability). The LED data sheet (assuming you are using blue or green) shows that at 2.5 V, the LED will draw ~ 1 mA. You could extrapolate to ~ 2 V and guess that the LED conducts less than 10 uA which would not be visible. You should still be OK with the calculations above. – jp314 May 8 '16 at 5:59