I am attempting to create a 32-bit shift register in Verilog with two inputs, DATA0 and DATA1. DATA0 is driven low to input a 0 to the register and DATA1 is driven low to input a 1 to the register. DATA0 and DATA1 are held high when they are not being used.
The issue that I am running into is when I drive DATA0 low, it replaces all of the bits in the register with zeroes. DATA1 works fine, shifting the register and adding a one to the end. My code is as follows:
module shift(
databits, //The register
reset , // reset Input
DATA0 , //Input for a 0
DATA1 //Input for a 1
);
//------------Output Ports--------------
output [31:0] databits;
//------------Input Ports--------------
input reset, DATA0, DATA1;
//------------Internal Variables--------
reg [31:0] databits;
//-------------Code Starts Here-------
always @(posedge reset or negedge DATA0 or negedge DATA1) begin
if(reset) begin
databits <= 0;
end
//If DATA0 triggered this, write a 0
else if (~DATA0) begin
databits <= databits << 1;
end
//If DATA1 triggered this, write a 1
else if (~DATA1) begin
databits <= { databits[30:0], 1'b1 };
end
end
endmodule
I tried using DATA0 to also input ones to the register, but it overwrote the entire reigsters with ones. It is my understanding that the always block should execute once when DATA0 goes low, so I do not understand why it is doing this.