So what is the difference between sr latch and level sensitive sr latch??
For sr latch, When 00, they just store the previous bit and when they are 01, the output q becomes 0, which they reset and when they are 10, the output q becomes 1, which they are set.
For example, if I have this level-sensitive sr latch:
how is the behavior different from the just regular SR latch??
There is only level sensitive or gated SR latch's. The other type of latch is edge triggered, also known as a flip-flop. Your diagram shows a SR latch with gated inputs.
In other words it can be set or cleared only if C (the gate control) is true and either S or R are true. If S & R are true and C becomes false, the output is unpredictable. A more simple SR latch would be just the 2 nor gates, using S1 and R1 as inputs, but other logic needs to make sure either S1 or R1 is false at all times. They are level sensitive in that the logic driving them must maintain a 'level or continous state until it is time to change.
By adding another gate to C input and tying it to the outputs you have a flip-flop, which trigger only on the rising or falling edge, yet still has S and R inputs to use if needed. Once the edge is detected, they maintain state until the next change using a rising or falling edge. Check this link for some details on the RS latch, as well as Wikipedia for flip-flops and 'D' latchs, which are used a great deal in many digital circuits.
Part numbers to look up for details:74HC02 nor gate, 74HC74 flip-flop, 74HC573 latch.
https://www.youtube.com/watch?v=VtVIDgilwlA
