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I was reading sunburst paper on Clock Domain Crossing and got stuck with this doubt.

enter image description here

Here in the 3rd flip flop, input is metastable state but at the rising edge of the clock output was set to high. In box they mentioned "clocked signal is initially metastable but sampled high on the next active clock edge" but no were in the document they are mentioning its reason. Please help me with this problem.

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  • \$\begingroup\$ Metastability has a sort of half-life time. It will fade away towards either 0 or 1. Unfortunately there is no upper limit on the amount of time it will take to do so, but the probability that it will survive for T decays rapidly with T. \$\endgroup\$ – Wouter van Ooijen May 10 '16 at 11:44
  • \$\begingroup\$ @WoutervanOoijen that means it can settle to either logic zero or logic one at next active clock edge based on half time? \$\endgroup\$ – tollin jose May 10 '16 at 11:52
  • \$\begingroup\$ It can. In a well-designed circuit the clock cycles are far enough apart with respect to the half-time, so the probability is (very) high. \$\endgroup\$ – Wouter van Ooijen May 10 '16 at 12:05
  • \$\begingroup\$ In this figure they got logic one at the output. Is it just an assumption ? it can settle to logic zero also. Right? \$\endgroup\$ – tollin jose May 10 '16 at 12:32
  • \$\begingroup\$ Yes. Or (on a bad day) it could still be metastable. \$\endgroup\$ – Wouter van Ooijen May 10 '16 at 13:02
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In the paper it is explained that metastability is inevitable in a system with asynchronous signals:

In a multi-clock design, metastability cannot be avoided, but the detrimental effects of metastability can be neutralized.

The picture you have uploaded shows the simplest solution, which is to use a flip-flop as a single "time delay" unit between the systems with different clock signals, to recreate a synchronized signal. As described here:

metastability may not always result in unpredictable output. If provided sufficient time with proper excitation, the f/f can in fact settle to a stable state

What happens in your picture is that the arriving signal is initially metastable. This generally means the signal is oscillating around a voltage that neither can be interpreted as 0 or 1. If it were used directly in e.g. a combinational logic, results would be inconsistent between parallel systems that use the data.

The time delay caused by the buffered flip-flops give it enough time to resolve its state to a valid voltage level, as metastability is very sensitive to thermal noises and other interferences (just like the example of a ball that is about to roll down a hill). It is only a passing state, never a final one.

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  • \$\begingroup\$ Stable state can be either logic zero or logic one. How they got logic one at the output (which is the correct value)? \$\endgroup\$ – tollin jose May 10 '16 at 12:35
  • \$\begingroup\$ Still am not able to understand. How you can say that metastability will settle to logic one? Why not logic zero? \$\endgroup\$ – tollin jose May 10 '16 at 12:55
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    \$\begingroup\$ @tollin I apologize, I seem to be mistaken about the metastable outcome. Refer to this question: electronics.stackexchange.com/questions/26981/…. The circuit avoids metastability propagation, stopping data inconsistencies. but does not perform miracles about guessing the correct state. \$\endgroup\$ – Vicente Cunha May 10 '16 at 13:31

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