Suppose there's two SDT_LOGIC_VECTOR signals A_READ and A_OUT, both 8 bits wide. A_READ is updated by some process at random intervals. A_OUT is connected to 8 LED's.

I want to blink a LED for each bit in A_READ that has changed since the last check. Checking interval should be fixed at around 10 milliseconds. LEDs should blink once for about 100 milliseconds.

How can this be done using a CPLD?


This is trivial. A_READ is registered at an interval of 10 milliseconds into A_READ_REG, then is checked for changes. To check for change on clock synchronous signals, you do edge detection. (A and not A_PREV ) or (A_PREV and not A). What have you tried that hasn't worked?

  • \$\begingroup\$ Should your question have been a comment? The tag and subject says vhdl not AHDL. \$\endgroup\$
    – user8352
    May 10 '16 at 17:36
  • \$\begingroup\$ Perhaps. What is AHDL? The question posed is a logic question, not really a vhdl question, and even so, unspecified enough for a more complete answer. \$\endgroup\$
    – Jotorious
    May 11 '16 at 16:33

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