How will this Verilog line be synthesized?

data = (s == 0) ? bus0 : 16’hz

The problem is that if I use mux/buffer it won't put Z if s!=0 because the output of the mux/buf is x (undefined) if the input is z.


I'll assume you're working in an FPGA. If you're talking about an ASIC, wait for an answer from someone who knows something about ASICs.

First, is data a wire or a reg, and is it connected to a pin? If it's a wire, the line should begin with the word "assign". If it's a reg, the line should be included in some kind of always or initial or similar type of block. It would also be better to use '<=' in place of '=' to get simulation to better match synthesis.

If data is an inout pin, this will synthesize as a tristate buffer.

If data is an internal register, this is probably not synthesizable code, unless you are working in a very old FPGA (XC4000 era or earlier?). What is actually produced is at the whim of your synthesis tool and might be different for different tools. It would be much preferrable to set to all 0's or all 1's, and then explicitly OR or AND together all the different drivers for the data bus.

In either case, if you are simulating this code, rather than synthesizing it, and there are no other drivers for data, the simulator is quite right to set the value to 'x', because there's no way to predict which way the tri-stated signal will drift in actual use.

Most simulators simply simulate the code exactly as it is, rather than guess what it will synthesize to and then simulate that. That means that un-synthesizable code will simulate perfectly well, even though they won't necessarily behave correctly when implemented in your FPGA.


You should not be writing code like this. Remember it is the compilers job to try and simplify the logic, your job is to be as clear as possible in defining the requirement , not trying to impress with 'clever' tricks. Also be clear that the compilers output may well vary depending on which set of tools and pre-compilers you use.

  • 3
    \$\begingroup\$ The ?: operator might be a "clever trick" in some programming languages, but in Verilog its often a necessity. In an 'assign' statement it's the normal way to indicate a decision, and it's more clear than whatever the alternative is in terms of &'s and |'s (which wouldn't even work when you want a Z result). \$\endgroup\$ – The Photon Dec 8 '11 at 6:12

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