# Design 5 bit counter with two control inputs (direction and stop)

I am designing a 5-bit counter with two control inputs including direction (up/down) D and stop S.

Here is how counter works:

DS = 00: down (or decrease)

DS = 01: don't care

DS = 10: stop

DS = 11: up (increase)

I tried this as the reference here by using 5 D flip flops and logic gates.

However, the result requires a lot of logic gates.

There are some questions I am not clear now.

1. For this problem, is there a way to know what kind of flip flops (SR, JK, D,...) will use the smallest number of logic gates?
2. I referred the method to solve this problem by drawing state diagram and then implementing it as the reference above.

However, because the large number of bits (5 bits), the implementation is complex and mistake-prone.

Also, are there any simpler counter that can do the task above?

• In addition to D and S input, there would be an edge-sensitive clock, right ? I can't see how you would count without a clock. In this case, why having a "stop" and "don't care" states ?
– dim
May 12 '16 at 20:42
• Have something to disconnect the clock to stop the counter, a couple of gates should do it (just a single AND would do it if you made 01 = count up and 11 = 10 = stop (1X)
– Sam
May 12 '16 at 23:44
• Thank you for help! @dim: Yes, there is a clock too. Sorry I missed that. stop: to stop the counter from counting. 01 is don't care because that input is impossible for my particular circuit. Tom: actually that way would work and I did try that. However, there is some problem when disconnecting clock when it is connected with other circuits. For that reason, I chose not use stop control input here. May 13 '16 at 0:42

If you use this specific chip, the input are a bit different than what you need: you have the $\overline{CTEN}$ pin which can serve as a STOP input (if it is 1, the count is inhibited), and the $D/\overline{U}$ input, which of course works the other way around from what you require. So if you can't change the specs of your D and S inputs, you need a bit of logic to adapt it to this chip. An inverter gate from your D input could provide $D/\overline{U}$, and if you do a XOR between your D and S inputs, you obtain $\overline{CTEN}$. Note: you can implement the inverter with a XOR gate, as well, if you hardwire a 1 to one of its input. So you can have a single chip that does the two operations.
Now, the chip I mentioned is only a 4-bit counter. But you can chain them. Just use two such chips and connect the $\overline{CTEN}$ input of the second counter to the $\overline{RCO}$ output of the first, and tie the clocks of both chips together, and the D/U pin of both chips together (see figure 2 of the datasheet). Now, you even have an 8-bit counter !