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I have 2 ICs working at 9 gbps. Output of 1 IC is differential CML pair and it goes as input to other IC. On PCB layout, if both ICs are placed on top (component) layer, one ICs positive pin is in front of negative pin of other IC hence positive and negative pins nets are making cross. How can these nets carrying 9 gbps differential CML signal making a cross can be routed? Is making vias a good option to go to another layer?enter image description here

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  • \$\begingroup\$ What kind of ICs? Many chips that deal with this kind of signal can be programmed to reverse the input or output polarity to avoid this problem. \$\endgroup\$
    – The Photon
    May 13 '16 at 14:58
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When it is only a single diff-pair, the typical solution is as follows, no layer changes required:

enter image description here

With many diff-pairs or large busses of signals, it may not be possible to keep all the tracks on a single layer. In these cases, you should do your best to minimize the number of layer changes (and hence vias), and control via impedances as best as possible. With a well designed ground plane and nearby companion vias, it is possible to design vias that preserve the trace impedance.

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  • \$\begingroup\$ Wouldn't the length difference between p and n nets make any difference in working? \$\endgroup\$ May 16 '16 at 6:48
  • \$\begingroup\$ You can add some squiggles to the shorter trace to equalize trace lengths. Your layout tool should be able to do this easily. \$\endgroup\$
    – uint128_t
    May 16 '16 at 14:08

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