An ADC capable of at least 1MSPS with a serial interface has to run serial interface at the sample rate * data width; many SPI interfaces can have variable word sizes of between 8 and 16 bits.
Normally, for ease of interfacing, 10 (12 and 14 as well) bit converters have a 16 bit data word with the unused bits padded.
I need at least MSPS sampling rate. When a serial ADC is rated with 1 MSPS sampling speed , is this done after considering the clock cycles required to shift the data sampled?
This is not how things are defined: take the sample rate and multiply by interface word size and the serial link must be capable of running at that rate. The actual interface rate has to include overhead (this is the catch-all term for extra bit times required to implement a serial protocol) so the actual interface clock speed will be a bit higher than the raw conversion data rate.
This may be faster than the controller is capable of (a common issue using bit banging of general purpose I/O pins).