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I am trying to interface an adc with an fpga, but I am running out of pins. I wanted to know if I use an ADC with a sampling rate same as the parallel one but with a serial interface , will I be compromising a lot with the speed ?

I need at least MSPS sampling rate. When a serial ADC is rated with 1 MSPS sampling speed , is this done after considering the clock cycles required to shift the data sampled?

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  • \$\begingroup\$ The speed of an ADC is defined by its sample rate. Assuming the same number of bits per sample, how you get that data out of the ADC, serial or parallel, does not matter. Is an oldfashioned parallel printer port on a 1990's PC faster than a modern USB 2.0 serial port ? No, the USB port is faster even though it is a serial data connection, it simply runs at a much higher speed than the parallel port. \$\endgroup\$ – Bimpelrekkie May 13 '16 at 6:53
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An ADC capable of at least 1MSPS with a serial interface has to run serial interface at the sample rate * data width; many SPI interfaces can have variable word sizes of between 8 and 16 bits.

Normally, for ease of interfacing, 10 (12 and 14 as well) bit converters have a 16 bit data word with the unused bits padded.

I need at least MSPS sampling rate. When a serial ADC is rated with 1 MSPS sampling speed , is this done after considering the clock cycles required to shift the data sampled?

This is not how things are defined: take the sample rate and multiply by interface word size and the serial link must be capable of running at that rate. The actual interface rate has to include overhead (this is the catch-all term for extra bit times required to implement a serial protocol) so the actual interface clock speed will be a bit higher than the raw conversion data rate.

This may be faster than the controller is capable of (a common issue using bit banging of general purpose I/O pins).

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As you pointed out difference between serial and parallel interface is mainly on the way they it sends data to Microprocessor and nothing to do with ADC conversion elements. Today if you chose either serial or parallel ADC with same sampling rate you will not be affected with sampling time, and as you know all major silicon vendors will have done enough calculation and practical analysis to make sure the the sampled data speed is effectively handled by the serial communication selected. And for ex, SPI has maximum transfer rate of 10Mbps this should be capable of handling ADC with sampling rate of 1MSPS.

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As a further note on this, there are many ADCs with SPI interfaces where sampling and conversion are tightly linked to the SPI transfer. This ensures you get maximum data throughput.

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  • \$\begingroup\$ This is indeed done, however If a converter or its sample and hold operates from the SPI clock, then any jitter on the SPI clock compromises the conversion quality. While if the sampling is triggered from the SPI select or start of word, any irregularity there will cause irregular sampling. \$\endgroup\$ – Chris Stratton Aug 24 '16 at 0:24
  • \$\begingroup\$ @ChrisStratton True enough. If you're using an FPGA though, you should be able to lock down the timing on the SPI bus pretty tightly. If you can produce a low-jitter sample pulse, then you can use the same techniques to produce low-jitter SPI clocks and chip selects. \$\endgroup\$ – Graham Aug 24 '16 at 11:54

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