# Crosstalk analysis, Altium vs. the World

I am trying to understand the real-world effect of crosstalk between nets, and I find I cannot match the data from abstract calculators (like Saturn's PCB toolkit and others) and the Altium crosstalk analysis.

For this sake I've made a dummy PCB project in Altium in which I purposedly placed the components very far away from each other and the tracks very close together (to maximize the crosstalk). See a picture of my PCB here:

It's a four-layer PCB with 1 oz. (35µm) copper on all layers, stacked like: signal, FR4 (0.3mm), GND, FR4 (0.85mm), VDD, FR4 (0.3mm), signal. VDD is 3.3V.

The analyzed tracks (SPI from MCU in the lower left corner to a memory on the upper right corner) are 0.15 mm. wide and have a 0.15 mm. gap between them.

Of course one shouldn't design boards that way. I should have so much trouble with a board like this.

So I used Saturn PCB Design's PCB Toolkit (a free tool) to calculate how bad my crosstalk should be:

Saturn PCB reports 2.64V of crosstalk for a nominal 3ns rise/fall time. My signals should be completely destroyed with such big a crosstalk.

I tried using Altium for the same analysis (a much more complete tool). I've applied the IBIS model to the CPU and generic IC (LV) models for the other two chips. Then I ran the analysis and got no errors. Here it is:

My surprise came when I generated a crosstalk analysis between the lines from the SPI group (SPI+CSEL), marking CSEL as victim and MOSI/MISO as attackers:

As you can see, Altium's analysis gives a much more optimistic data of the crosstalk, amounting to mere +/- 75 mV, instead of 2.64V I've expected.

Elsewhere I've read that Saturn PCB calculation has the wrong picture to illustrate the parameters, and the (S) parameter should be the distance between track centers and not between track edges. That would rise the distance from 0.15 mm. in my first calculation to 0.30 mm. Although the crosstalk is milder, the new data is not significantly closer to Altium's analysis:

So I am clearly missing something here. First, what would the right value for Saturn PCB's (S) parameter be? 0.15 or 0.30? And more importantly, why Altium gives us values that are orders of magnitude lower than Saturn's? What am I doing wrong?

Please find attached the Altium project and it's generated output (schematics, Gerbers, etc.) for reference.

Project and project outputs

• I'm not sure how the Saturn tool can be using the distance-between-centers as the S parameter, since it never asks you the trace widths. Commented May 13, 2016 at 16:52
• The rise time in the Altium analysis looks a good deal longer than 3ms nom to me. Commented May 13, 2016 at 17:04
• +1 Good question, well formatted, presented findings, and provided source files. I wish all questions were done like this. Well done! Commented May 13, 2016 at 17:24
• @ScottSeidman The rise time in Altium is at most 3ns at the attackers' outputs, and about 2ns at UM3-5 MOSI (5th plot). Commented May 13, 2016 at 18:43
• Have you tried reducing your track height? 0.3mm is almost an entire order of magnitude larger than typical 1oz copper. Solving for the same inputs but with a Conductor height of 0.03556 mm gives a coupled voltage of 0.04572V, which seem much more reasonable. Commented May 14, 2016 at 15:31