I want to simulate the scrambler/descrambler device provided in ITU-T Recommendation V.27, but the circuit diagram has some weird logic gates I can't make sense of. I'm talking about those "÷32", "÷2" and "\$t_d\$" gates (circled red). As far as I understand, "÷32" and "÷2" gates are supposed to be clock signal dividers, but if so, what do the bottom pins do and what's "\$t_d\$" for? Is it a time delay? It reads so, but the whole purpose of them looks too cryptic to me and I am not sure what gates should I use, say, in Protues to correctly emulate this thing.
What you call an ":" is a divide symbol, NOT a ":".
Below Divide = "/". :
So /32 = divide by 32 = 5 stage counter.
Each stage divides by 2 in a binary counter (eg CD4040) so for 1 2 3 4 5 stages the divide ratio is 2 4 8 16 32.
/2 is a one stage counter = a flipflop configured to toggle when clocked.
The bottom lines do what the labels says = reset line.
The dividers are reset to 00000 and 0 respectively.
The box labelled "td" is explained in note 2 - it's a time delay - read the note.It's not complicated - it means EXACTLY what it says. ie there is a delay due to physical circuit parameters.
The 2 divider blocks are divide by 32 and divide by 2. That is simply implemented by a 5 bit binary counter (div32) and a D flip flop with \$\overline Q\$ tied to the D input.
The purpose of the time delay is explained in note 2 and is to ensure reset is not asserted too early.
The delay should be greater than the gate delays of the path from H at the shift register to the delay block. This is the sum of the delays from the clock asserting at the shift register to its outputs updating, plus the longer of the delays from bits 9 and 12 through the gates to the delay block.
Most simulators have a simple delay function ( I am not a Proteus user, so I cannot say what it can use).
Note that the circuit diagram is using assertion level logic