I Prepare for Entrance Exam on PhD, CS Filed. I ran into a previous question with following options (A to D from one to forth lines):
The question is:
if the input is always has valid values (no invalid inputs), the the second line is True, How Can help me how this will be reached ?!
If \$c=0\$, then the top tri-state is hi-Z. The lower tri-state must be on (\$a=1\$) for the output to be well-defined, so \$out=c=0\$.
If \$c=1\$, then the top tri-state is enabled and:
a. \$a = 0\$ so that the bottom tri-state is off and \$out=a\cdot b = 0\$; or
b. \$a = 1\$ and the top and bottom tri-state must have the same output for the state to be valid, that is to say, \$\overline{c} = \overline{a\cdot b}\$. Given the known values, \$b = 1\$ is required and \$out = 1\$
This analyses all possible valid combinations (based on the valid possible configurations of the tri-state buffers). We can see that the output is 1 when \$a\cdot c\$, and 0 otherwise. Thus,
\$out = a \cdot c\$
This is perhaps not the most efficient way of analysing it, or the most generalisable (truth tables and then a Karnaugh map reduction would be more general), but it seems a better approach to understanding what's going on intuitively.
Point b above is potentially dangerous in actual implementation, due to shoot-through in the case that \$a = c = 1\$ and \$b = 0\$.
There are eight possible input states, of which three are invalid: (a,b,c) = (0,0,0); (0,1,0); and (1,0,1). The first two of these give a high impedance state at the input to the final inverter, and the third gives a 0/1 conflict at the final inverter input.
Construct the truth table and it's clear that \$out=a.c\$ is the correct answer.
a.b\$\endgroup\$ – Jasen May 15 '16 at 7:44