1
\$\begingroup\$

I made a simple simulation of following circuit (in LTSpice): enter image description here

The IRFZ44N mosfet (10v on gate voltage) is switched on and off with 1kHZ 12V 50% duty cycle PWM signal. The "Heavy-load" is just a passive, 1 Ohm resistor.

I got following simulation result: enter image description here

Why does the vout voltage reach just 7V (I expected something around 12V, since fet should be fully on)? Why is the load current (I heavy load) so much non-linear curved cycle?

\$\endgroup\$
  • \$\begingroup\$ 7 V limit was already explained by Peter Smith; I am still curious about exponential-like curves in the simulation results. Definitely wrong behaviour for this circuit. Seems to be the result of the incorrect simulation setup or an incorrect device model, but I am unable not find an error. Such behaviour may be observed if the PWM source switches to high-Z state during off-time (not so in the circuit, as I can see). \$\endgroup\$ – dmitryvm May 15 '16 at 15:55
  • \$\begingroup\$ The exponential curves are when the gate drive is switched off and is probably due to the natural RC discharge of the FET. \$\endgroup\$ – Peter Smith May 15 '16 at 18:34
  • \$\begingroup\$ @Peter Smith: True, but how can it happen in this circuit? PWM voltage source should pull the gate to the ground. I have tried to reproduce such behaviour with LTspice. No exponentials, sharp turn-off as expected. \$\endgroup\$ – dmitryvm May 15 '16 at 19:09
  • \$\begingroup\$ Something for me to look at in the morning :) \$\endgroup\$ – Peter Smith May 15 '16 at 19:11
4
\$\begingroup\$

You have put the load in the source; as the gate voltage must be above the source by a few volts to switch the device on (N channel enhancement mode MOSFET), the source cannot rise above (in this case) 7V. As the source voltage approaches \$V_{gs}\$ at a level to support 7A, it simply cannot drive any harder.

If you put the load between the drain and the 12V power and tie the source to ground, you should get the results you expect.

Here is a circuit that implements it, and it simulates as I would expect:

IRFZ44N properly connected

The plot:

Circuit response

The simulation model must be in the same directory as the simulation circuit; make sure you set up the FET properly:

Hover the cursor over the FET and CTRL Right click to get this:

Setting up a subcircuit

It is important that the prefix is 'X' as this indicates to LTSpice that the model is a subckt.

\$\endgroup\$
  • \$\begingroup\$ where do I have to put *.spi file to be able to include it like you did? \$\endgroup\$ – Lukasz May 15 '16 at 15:59
2
\$\begingroup\$

To turn the FET on fully its Gate voltage must be 10V above the Source voltage. But in your circuit the Source is connected to the load, so to get 10V between Gate and Source and 12V at the load your PWM needs to be 10V+12V = 22V. With only 12V the FET will start to turn off as the load voltage rises and subtracts from the Gate-Source voltage.

Here's your circuit rearranged to have lower voltages towards the bottom:-

schematic

simulate this circuit – Schematic created using CircuitLab

To keep the FET turned on you must apply 10V above the supply voltage. This is a big problem if you only have one supply, as you need a voltage booster to generate the extra voltage. If you always apply PWM with less than 100% duty cycle then the square wave at the load can be coupled through a capacitor to 'bootstrap' the Gate-Source voltage. Many FET driver ICs use this technique (eg. IR2101). If the load may be turned on permanently (100% PWM) then you need an independent high voltage. Some drivers have a voltage booster circuit built in (eg. LTC1255).

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.