# Metastability error propagation with flip flop

I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain crossing boundaries, but my confusion is that the output of metastability is unpredictable, it might lead to high or low level, and that output then will be propagated to the rest of the circuit, so how can the second or the third flip flop catch the right value to be transmitted , if the first flip flop is always at metastable state and might settle in a wrong level ?

The first FF is not always metastable. Assuming that input edges are uniformly distributed with respect to its clock, the first FF has a certain probability of going metastable that is related to the clock period and its setup/hold time requirements. If it does go metastable, it resolves itself within some amount of time — the probability of remaining metastable after time t is an exponentially decaying function of t.

The second FF has a much lower probability of going metastable, because it would have to get clocked at just the right instant when then first FF (if it was metastable) happened to be resolving itself. Otherwise, its output will be either definitely high or definitely low. The signal change might be delayed by an extended metastability of the first FF, but it is very unlikely to cause the second FF to go metastable and adversely affect the operation of the rest of the logic.

A third FF reduces the chances of metastability to infinitesimal levels.

• You have the only rational answer if 'D' is asynchronous to the clock on the first flip-flop. It becomes the 'synchronizer' for down-stream stages, which have a metastable probability close to zero.
– user105652
May 17, 2016 at 23:13
• Thanks Dave, when the first flip flop go metastable , resolving itself means it will be high or low level after a certain amount of time , is this level identical to the original flip flop input ,or it might be wrong and then propagated to all the circuit May 18, 2016 at 19:19
• @HachaniAhmed. If the first flip-flop enters a metastable state where D = '1', but Q = '0' (after settling down), then the first stage has output the wrong logic value. That is why the first stage of a data synchronizer has an uncertain output. Its effect changes the un-synced value probability from +1 error/-1 error to a +1 error only. To filter this out takes at least a 2 pole digital filter for both logic '1' decisions and logic '0' decisions. A one stage flip-flop is always metastable prone to async inputs. If it is oversampling at a fast rate then metastable is more likely.
– user105652
May 18, 2016 at 20:36
• @HachaniAhmed: When a FF goes metastable, it could resolve either way. But if it resolves the "wrong" way, all that means is that you have delayed detecting the change on the input by one clock period -- no real harm done. It's the same result you would have gotten if the raw input signal had been just a little bit later than it actually was. If it resolves the "right" way, that just means you got lucky and detected the change one clock sooner than you otherwise might have. May 18, 2016 at 21:38
• No harm is done, because the"wrong" value is simply the old value. The circuitry downstream from the synchronizer has the same behavior either way, just one clock later. Regarding MBTF, the first"failure" ends when you build the circuit and turn it on the first time. May 19, 2016 at 15:22

When you have a metastability scenario, that is the input signal changes at exactly the sampling clock edge, both 0 and 1 are correct values. What is important is all the subsequent logic sees the same value (assuming your victim signal fans out to several ultimate capture points). If the clock edge had been slightly earlier or later, you would get a clear 0 or 1, so it should be reasonable that you can't precisely chose one or the other to be the correct answer.

The cascaded flops will be more and more likely to resolve to a stable value within a clock cycle, so the output of the sequence ought to be static (for a static input), or transition within +/- one cycle of the input transition plus 2 or 3 cycles depending if its a double or tripple sync.

A side effect of this is that wnen several signals are sampled asynchronously (or without clear setup-hold), you need to anticipate all of the potential race conditions, and not rely on seeing the changes in the same cycle-precise combinations that they were generated.

• Your first sentence is confusing. '0' and '1'? Your answer does not include the benefits of oversampling even on parallel async inputs, which gives time to align async data by the 3rd stage. The second stage determines and corrects for minor (1 cycle) skewing of the data. The first stage removes only the major metastable component. The 3rd stage output should be aligned and synced to the data clock.
– user105652
May 18, 2016 at 2:03
• You are applying your concept of how it ought to work to my answer. Consider, t=1, the input is 0. t=2, the input is 1. If you sample at t=1.5, what value do you functionally expect? Its not defined, and depends on the timing of the path. Worst case, its mid rail, and the output of the first flop either rises, and collapses, or rises slowly and stays high. So, expect with equal probability, a 0 or a 1 value to result from the input transition. May 18, 2016 at 7:51
• You should have made it clear you were speaking of probabilities and not implicit logic.
– user105652
May 18, 2016 at 20:45