I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain crossing boundaries, but my confusion is that the output of metastability is unpredictable, it might lead to high or low level, and that output then will be propagated to the rest of the circuit, so how can the second or the third flip flop catch the right value to be transmitted , if the first flip flop is always at metastable state and might settle in a wrong level ?
The first FF is not always metastable. Assuming that input edges are uniformly distributed with respect to its clock, the first FF has a certain probability of going metastable that is related to the clock period and its setup/hold time requirements. If it does go metastable, it resolves itself within some amount of time — the probability of remaining metastable after time t is an exponentially decaying function of t.
The second FF has a much lower probability of going metastable, because it would have to get clocked at just the right instant when then first FF (if it was metastable) happened to be resolving itself. Otherwise, its output will be either definitely high or definitely low. The signal change might be delayed by an extended metastability of the first FF, but it is very unlikely to cause the second FF to go metastable and adversely affect the operation of the rest of the logic.
A third FF reduces the chances of metastability to infinitesimal levels.
When you have a metastability scenario, that is the input signal changes at exactly the sampling clock edge, both 0 and 1 are correct values. What is important is all the subsequent logic sees the same value (assuming your victim signal fans out to several ultimate capture points). If the clock edge had been slightly earlier or later, you would get a clear 0 or 1, so it should be reasonable that you can't precisely chose one or the other to be the correct answer.
The cascaded flops will be more and more likely to resolve to a stable value within a clock cycle, so the output of the sequence ought to be static (for a static input), or transition within +/- one cycle of the input transition plus 2 or 3 cycles depending if its a double or tripple sync.
A side effect of this is that wnen several signals are sampled asynchronously (or without clear setup-hold), you need to anticipate all of the potential race conditions, and not rely on seeing the changes in the same cycle-precise combinations that they were generated.