Gate driver and instability problem

This is a gate driver circuit for a boost converter. However, there is one part that I don't understand. Could you explain it or give me some links so I can read up about that?

Here is the part that is confusing:

The addition of several stages to the driver introduce a propagation delay between the input and output signals. This delay degrades the control loop phase margin and may lead to instability. To counteracts this effect the drivers logic gates connected in cascade should be progressively scaled.

I don't understand why delay degrade phase margin and why scale these gates like that will solve the problem. Thank you very much for help.

• Maybe you could point out what exactly it is you did not understand, since I could write books elaborating that whole paragraph and image... – PlasmaHH May 18 '16 at 11:20

The switching transistors Ml and Mu are generally very large, they may have a gate-source capacitance of a few pF. On chip, that is a lot. If you would try to turn those transistors on/off with a simple standard as-small-as-possible inverter then that inverter would have a hard time because of the enormous load of these large switching transistors.

It is the same as in digital logic where you have a certain fan-out a logic gate (like an inverter). One inverter can only drive 5 inputs for example. If you want to drive more then you can expect delays for which you have to account or you could use an inverter with a larger output drive, for example one that can drive 20 inputs.

It is the same for driving these large switching transistors, you cannot drive them from a single small inverter as it would take very long for the small inverter to charge/discharge the gate of those large switching transistors. And for efficiency, you want fast switching in DCDC converters. So we take a small inverter, let that drive a larger one and that one drives an even larger one all the way up to a very powerful and large inverter that can drive the gates of those large switching transistors directly.

The switch driver circuit you show is actually something different, it's a break-before-make circuit. It will only switch on Ml when Mu is off and the reverse Mu can only be on when Ml is off. Without this circuit it would be possible for both large switching transistors to be on at the same time, shorting Vdd to ground. You want to avoid that !

The phase-margin story probably has to do with an alternative to the break-before-make circuit. You could achieve a similar effect by just waiting a certain time for the other transistor to switch off before switching on a switching transistor. However, since you would need a long enough delay to be sure that the other transistor is off, there will be a longer time when both transistors are off (because some margin is needed) compared to the situation when you would use the break-before-make circuit. This longer time when both transistors are off lowers the loopgain of the DCDC converter's control loop. This is a complex subject, if you do not understand this then please read a book about it. You will also need some understanding of feedback systems in general.

• I think you meant break before make :) – Peter Smith May 18 '16 at 12:47
• @PeterSmith Oops ! At least someone was paying attention (you), I will update the text. – Bimpelrekkie May 18 '16 at 13:33
• An excellent description of the issue. The OP may need to be guided to why dead time is necessary. – Peter Smith May 18 '16 at 18:47

Over all the circuit is trying to prevent the PMOS and the NMOS from being turned on at the same time, this is called "shoot-through" current and since these are big transistors this effect can be very large. This current would be wasted instead of going to switching the load.

As an useful exercise just do a timing diagram with delays.

The added delay adversely affects the phase margin of the controller so the delay must be minimized. The minimal delay in any given process is one when you have the gates scale larger as they get closer to the load.

To see why, just imagine the little logic gate driving the big transistor, the logic gate has minimal current drive, so it will be slow. There is a optimal number of stages and an optimal current drive scaling at each stage that will determine the smallest delay.