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I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output of a module to be either 0 or 1 (don't care) when not on and the product of inputs when on. Assume that once the module goes on, it cannot go off unless reset. The code with operand isolation I think would go something like this...

module some_module(input clk,rst, input on, 
input [3:0] in1, in2, output reg [7:0] out);

reg state_ff;
reg [3:0] isol_in1, isol_in2;

// Make inputs change only when on (Isolation)
always @* isol_in1 = !state_ff ? 0 : in1; // When state=0,isolate inputs.
always @* isol_in2 = !state_ff ? 0 : in2;

always @*
 out = isol_in1 * isol_in2; 

always @ (posedge clk)
if ( rst ) 
     state_ff <= 0;
else case ( state_ff ) 
     1'd0: state_ff <= on;     // After reset, wait for on = 1.
     1'd1: state_ff <= 1'd1;   // Needs reset to turn off.
     endcase

endmodule

I'm assuming AND type isolation in the above code. When the unit is off (on = 0 since reset), transitions on the input will not be seen by the logic so will prevent unnecessary transitions in the multiplier. Does this actually save any power (assuming several other modules are being driven by in1 and in2)?

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1 Answer 1

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This might save toggle power, but only in this module, and only before this logic is used once. You've spent a flop doing that, and added some gates. I don't think this is useful (but I don't have visibility of your whole system).

You would be better off clamping the in1, in2 at source, and more frequently. Even better is gating the clock to a clop that drives them (you only need a single AND, plus it saves both clock and signal toggle power)

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