Are rise/fall times typically affected by the clock speed. That is if I have a AVR at 16 MHz will it have a different rise/fall time than the same AVR at 32kHz?


This is usually called "drive strength" or "speed" and is configurable in some microcontrollers like STM32 and Altera FPGAs.

In general, the edge-rate is not controlled by clock speed.

Edge rate (or slew rate as Ben points out) is controlled by the source impedance of the driver, rather than the oscillation speed. Because edge rates can be so much faster than the clock rates, sometimes you want to limit it by changing the internal drive setting or by placing series resistance into the line to reduce RF emissions.

The edge rate has to be fast enough to get to full amplitude during a cycle for a fast clock speed, but otherwise there isn't any real limit on how fast or slow the edge rate is in comparison to the clock rate. Edge rate and clock rate are the result of different physical processes and circuitry.

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    \$\begingroup\$ Another common term is "slew rate" \$\endgroup\$ – Ben Voigt May 20 '16 at 2:16
  • \$\begingroup\$ Why is it not controlled by clock speed?? \$\endgroup\$ – Jasser May 20 '16 at 2:29
  • \$\begingroup\$ If the clocks originate from the same xtal and divider chain and logic gates, they will produce the same rise/fall times. \$\endgroup\$ – VTNCaGNtdDVNalUy May 20 '16 at 3:54
  • \$\begingroup\$ @Jasser Because, edge rate is not directly related to the cycle time of the clock. \$\endgroup\$ – Daniel May 20 '16 at 3:59
  • \$\begingroup\$ @Sparky256 That is explicitly wrong. \$\endgroup\$ – Daniel May 20 '16 at 3:59

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