I need a clock source for some data converters (DAC, ADC), and I would like the clock frequency to be as configurable as possible. I assume this would involve some kind of clock multiplier/divider, PLL, etc. The range of frequencies I would like to be able to configure at runtime would be something like 200ksps up to about 20Msps (one clock cycle per sample). I don't need extremely tiny frequency steps in this range.
The ideal answer would reference specific part numbers with detailed reference designs. I can deal with single ended or differential clocks. Configuration of the clock generation would most conveniently be with 3.3v CMOS logic, though level translation is certainly a viable option there.