Rather new to electronics, I'm trying to design some of my first circuits. One of them includes a bridge rectifier feeding into an opamp used as a comparator. However, I'm a bit perplexed as to why LTSpice shows the input voltage as consistently negative, regardless of where in the sine wave the input voltage component is at/should be. I've tried reversing the polarity of the voltage component, reversing the leads that feed the bridge, and the like but seem to get the same result. The input voltage is above zero at about +1V (I'm assuming due to 2X the voltage drop of the diodes used) for part of the cycle - inverting the concept of a diode "voltage drop". Is the voltage really driving negative or is this an artifact of LTSpice modeling? In either case, is there a way to change this?
To answer your follow-up question Jim, if you move the ground to Vrin2, Vrin1 will be a sinewave at 0v dc offset. But there is another way to see the sinewave, and that is with mathematical plotting.
- Right-click the chart, choose "Add Trace".
- In "Expression(s) to add" type in: V(vrin1)-V(vrin2)
- Shorthand: click V(vrin1), press -, click V(vrin2)
Note that the voltage source is ideal by default, so has no resistance, thus will produce a perfect sine wave. Expect real-world measurements to never match simulation. So here is added 1Ω of series resistance, and a capacitor chosen with real-world parasistic values (a good 25v Nichicon):