Routing layer 4 showing differential trace between ground vias

I have ground vias underneath an ADC on a multi-layer board for thermal relief. I am using inner layers to route the LVDS signals for the ADC. The image shows diff pairs on layer 4, which is in between plane layers. Do the ground vias have any effect on the diff pairs, even though the vias are not connected to layer 4? If so, is the pair at the bottom more susceptible since only one half of the pair is adjacent to ground vias?

Due to space constraints, I cannot avoid routing underneath the ADC region. So what I have done is use routing layers that are farther from the surface layer and that are in between planes. Any suggestions will be appreciated.

I looked up other threads regarding thru vias and diff pair routing rules, but could not find something that addresses this.

  • \$\begingroup\$ The issue is that there will be copper voids around the vias. In order for the traces to couple to a plane, there should be copper on the plane layer between the edge of the trace (on adjacent layer) and the via clearance hole. What is the circle, exactly? The via hole, or ??? We need to see what the copper layers actually will look like (maybe generate gerbers). \$\endgroup\$
    – user57037
    Commented May 21, 2016 at 1:48
  • \$\begingroup\$ Sorry, I cannot provide gerbers. However, layers 3 and 5 are solid ground planes. The circle represents the via hole positions and the green line is the ADC outline. So as long as layers 3 and 5 are ground planes, which is what the thru vias are connected to, then this is OK? \$\endgroup\$
    – JackOTrade
    Commented May 21, 2016 at 2:05
  • \$\begingroup\$ I know they are vias. When you put a via through a plane, and they are not connected, there will be a copper void in the plane around the via to make sure the plane does not short to the via. It looks like that void area may extend very close, or even overlap with your traces. This means that the trace will not be referenced well to the plane in that area, because it is over void, not copper. It is considered bad for signal integrity and EMI. I would also be concerned about the traces adding noise to your ADC inputs. But that is another issue. \$\endgroup\$
    – user57037
    Commented May 21, 2016 at 2:20
  • 2
    \$\begingroup\$ @mkeith from the ObiWan's comment, it seems that there isn't going to be a void in the ground plane around the vias as the layers of plane are connected to them. But I agree that the presence of the via itself may cause issues if it is too close - how bad it will be will depend on the speed, but LVDS itself tops out at around 1Gbps (maybe 1.2G at a push), which is still low enough that it's relatively forgiving. I wouldn't do it though - best to keep anything digital away from any analogue front end. \$\endgroup\$ Commented May 21, 2016 at 2:28
  • 1
    \$\begingroup\$ @mkeith, no worries. Thanks for the prompt responses. \$\endgroup\$
    – JackOTrade
    Commented May 23, 2016 at 4:17

2 Answers 2


You may be trashing the ADC's VDD lines or REF lines, or trashing the sampling clock (causes jitter, ruining the noise floor).

Assuming 1mm by 100micron coupling area (parallel-plate model) with 100micron spacing, and ER=5, the capacitance is C = E0*Er*Area/Distance. The 100micron / 100micron cancels, thus C is 1e-11F/meter * 5 * 1mm = 50 femtoFarads. With 1nanosecond edge to the LVDS, and 0.2v swing, or 0.2v/nS, the induced current is (I = C*dV/dT) = 50e-15F * 0.2v/1e-9s = 50 * 0.2 * e-15 e+9 or current is 10*e-15+9 = 10e-6 =10uA with rise time of ?? 100 picoseconds? Into bypass caps with 1nH inductance, the upset voltage is V=L*dI/dT or V_cap_upset = 1nH * (10 * 1e-6)/100pS == 1e-9 * 1e-5/1e-10 = 1e-14 * 1e+10 V_cap_upset = 100 microVolts. Can you live with that, occurring on EVERY BITTIME of the LVDS?


It seems that your LVDS lines are quite close to those vias. Additionally it is not clear how long they are from source to load. I explain why.

From a book on RF measurements & pcb design I wrote a few years ago, a common estimate of via parasitic capacitance is from the snapshot below. enter image description here

Self capacitance for vias located on the line traces is larger than coupled capacitance for vias next to the line (of course). Note that you have 5 vias, so capacitive loading is 5 time larger, and that the distance from LVDS traces is small (less than 1 via diameter), so coupling is not negligible. As a rule of thumb mutual capacitance may be in the order of 1/3 - 1/5 of self capacitance: to calculate it more accurately...

The effects of capacitance for step-like and pulse-like signals are:

  • reduced impedance terminating the line during waveform edges; lower characteristic impedance values give a more comfortable limit of tolerated stray capacitance: an overall 1pF of capacitive loading on a Zc=50ohm line gives 100 ps limit; this means that a 0.2 ns LVDS may slip into troubles if Zc goes up to 100 ohm, as it is ...
  • capacitive loading of line sections causes additional delay for signal propagation; this creates ringing during transitions and depending on line length there may be just an "echo" or a nasty superposition; the added delay is 2.2 time constants, that is 2.2 Cp Zc; for common values it amounts roughly to the rise time.
  • for a differential line as LVDS is, separation of vias similar to gap between traces causes common-to-differential mode transformation, so immunity of your LVDS is a bit challenged.

I see that the two LVDS lines are not loaded in the same way.

If ADC thermal vias can be blind and finish at some first ground plane inner layer, than LVDS traces in a lower layer will see only the void of dielectric material, that is much better than being sided by vias going top to bottom.

Ref [199]: H.W. Johnson and M. Graham, High-Speed Digital Design - A Handbook of Black Magic, Prentice Hall, Englewood Cliffs, New Jersey, 1988.


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