Conceptually yes, but in terms of sourcing, probably not, and anyway, sourcing is an off-topic shopping question.
But to explain the conceptual issue, the receive path of a UART typically operates by oversampling rather than by clock recovery. Your calculations assume 8x oversampling, which is the lower of the two typically used values of 8x and 16x.
However, the transmit path does not require much in the way of oversampling as it is fundamentally free to dictate its own timing - it is not trying to detect the timing of the other end in the way a receiver does. Having a clock of 2x the baud rate could potentially be convenient, and it is probably required that the clock rate be an integer multiple of the baud rate, but is does not need to be 8x. 2.4 KHz probably works conceptually.
However, you may not find an off-the-shelf IC with this capability. A custom implementation in an FPGA or largish CPLD should be possible.
It might also be possible to build an FPGA based receiver using 7x rather than 8x oversampling.
You could also consider if a baud rate of 1125 (9 KHz/8) might be tolerated by a given receiver configured for 1200 baud. Dropping the effective baud rate even below the intended deviation might be a useful test.
By careful manipulation of data patterns, it might also be possible to (ab)use an SPI engine to transmit a UART-compatible data waveform at a closer fraction of its clock rate, though you would probably need to run it in a greater than 8-bit mode.