I am new to CMOS technology and I am trying to learn about CMOS logic gates. I have a problem with transistors sizing. As far as I could understand the main idea is to obtain equal rise and fall times. But, for example, how can one achive such thing on a NOR gate? If both nMOS transistors are ON the capacitor will be discharged faster than if only one of the nMOS transistors were ON. Have I understood something wrong?
Here is the NOR that is probably being referred to:
In the state where both C&D signals are high both of the lower NMOS transistors are on and thus discharge the "Out" node faster than a single NMOS could (in the case of when only one of C or D is high).
Basically you don't worry about it, because there are other more dominant effects. And to fully get the fastest effect both C & D must arrive synchronously within the rise time (ps for advanced processes).
The bigger issue arrises in the case of the upper PMOS transistors which are ~ 2.2X slower than the NMOS and are thus the limiting factor for the highest speed. Because they are in series, in order to match these transistors the Widths must be 2X (series) 2.2X (conductance) = ~ 4.5X wider for the same Gm. This greatly dominates the area used as well as the Fan-in numbers. This fan is effect will be a dominant effect as well.
Any associated timing numbers (propagation delays) are numbers that must be met, or are guaranteed. If the device switches faster in certain conditions then it doesn't matter and is not designed for.
Or you can use a different structure.
In such a case you have to consider the worst case, i.e. only one transistor active in the pull down network and of course you have to account for the series connection of two PMOS transistors in the pull up network.
The design should use the inverter as reference for the worst case, so that you have equal delays.
Of course for some transitions the gate will be faster than the inverter.