0
\$\begingroup\$

I am new to CMOS technology and I am trying to learn about CMOS logic gates. I have a problem with transistors sizing. As far as I could understand the main idea is to obtain equal rise and fall times. But, for example, how can one achive such thing on a NOR gate? If both nMOS transistors are ON the capacitor will be discharged faster than if only one of the nMOS transistors were ON. Have I understood something wrong?

\$\endgroup\$
2
\$\begingroup\$

Here is the NOR that is probably being referred to:

enter image description here

In the state where both C&D signals are high both of the lower NMOS transistors are on and thus discharge the "Out" node faster than a single NMOS could (in the case of when only one of C or D is high).

Basically you don't worry about it, because there are other more dominant effects. And to fully get the fastest effect both C & D must arrive synchronously within the rise time (ps for advanced processes).

The bigger issue arrises in the case of the upper PMOS transistors which are ~ 2.2X slower than the NMOS and are thus the limiting factor for the highest speed. Because they are in series, in order to match these transistors the Widths must be 2X (series) 2.2X (conductance) = ~ 4.5X wider for the same Gm. This greatly dominates the area used as well as the Fan-in numbers. This fan is effect will be a dominant effect as well.

Any associated timing numbers (propagation delays) are numbers that must be met, or are guaranteed. If the device switches faster in certain conditions then it doesn't matter and is not designed for.

Or you can use a different structure.

\$\endgroup\$
  • \$\begingroup\$ Do you know any good books to read about digital design, logic gates and CMOS? \$\endgroup\$ – SebiSebi May 21 '16 at 20:07
  • 1
    \$\begingroup\$ a note, modern processes have fully depleted channels, and the p/n drives are identical. The 2.2x was true above micron sizes, but as we've tried to scale behavior, it's become less so because the higher order effects dominate in the n+. You'll see 1.8x on 130nm, and the p-n ratio just slides down from there until you hit fully depleted channels. My last 14nm SOI run actually have the pfets slight stronger than the nfets. Of course, it just depends on how the fab sets the cook. \$\endgroup\$ – b degnan May 21 '16 at 20:40
  • \$\begingroup\$ @bdegnan the 2.2X factor arises from mobility differences, and is fixed. Gm differences will track this unless it is designed out or other effects come to bear. I don't disagree with you about the changing Gm ratios but you do contractdict yourself, 130 nm is NOT above 1 um. You are ignoring the fact that is DSM processes that a lot of this mis-matched was deliberately designed away through the use to lateral strain. I just noticed that I grabbed a picture without bulk connections so I'll change that, I was wondering what you talking about SOI for ... \$\endgroup\$ – placeholder May 22 '16 at 14:10
  • \$\begingroup\$ @SebiSebi I will note, that in the future, when you ask questions you really need to be more clear. In this case a schematic was mandatory. the fact that I drew it probably saved you from being closed. There many different ways of making logic gates, so you can't assume people will know what version you are talking about. \$\endgroup\$ – placeholder May 22 '16 at 14:26
  • \$\begingroup\$ @placeholder Your assumption is based on doping levels for mobility without higher order terms. The 130nm point I made just because it's empirical. The mobility loss due to impact ionization is higher with n due to mean time to collision. You will also note that I specifically mentioned fully depleted channels. The 0th order rules of thumb no longer apply; it is no longer 1990. \$\endgroup\$ – b degnan May 22 '16 at 14:54
1
\$\begingroup\$

In such a case you have to consider the worst case, i.e. only one transistor active in the pull down network and of course you have to account for the series connection of two PMOS transistors in the pull up network.

The design should use the inverter as reference for the worst case, so that you have equal delays.

Of course for some transitions the gate will be faster than the inverter.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.