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Recently, I've installed Altera Quartus 15.1 and now follow the "getting started" instructions, you can read it here. At the step: to see the resulting circuit go to Tools →Netlist Viewers →Technology Map Viewer (post-mapping). After going there I get the following scheme: enter image description here

Instead of much more demonstrative diagram from the tutorial:

enter image description here

Here is the code:

// file lab1.v
module lab1(SW,LEDG);
    input [1:0]SW;
    output [1:0]LEDG;
    // input SW*, output LEDG*
    hadd myHalfAdder(SW[0],SW[1], LEDG[0], LEDG[1]);

endmodule

// file hadd.v
module hadd(a,b,cout,s);
    input a, b;
    output cout, s;

    assign {cout,s} = a+b;

endmodule

There are too much groupings and no view of underlying gates. I can't figure out how to adjust the view so it will be similar to what I see in the tutorial. Any suggestions?

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It's changed over time. It used to look like the bottom picture about 8 versions of Quartus ago. Now it looks like the top picture. However you can still view the logic, it's just not in the same place.

The reason so far as I can tell is that FPGAs are getting more and more complex, and at some stage it becomes simpler to show the entire logic cell (which may be up to 8 inputs, with adders, carry chains, etc.) as a black box, than to try and split it up into a diagram of gates. Drawing out the contents of every LUT in a huge design would take a lot of time.

It is possible to see what each LUT represents in the technology map, but not inline like in the bottom diagram. Instead you view it in the properties view:

Equation View

If you double click on the block (or right click on it and select "properties"), a window appears to the left which shows information about the LUT. There are two places in this window that you can find info about the contents.

Firstly, if you go to the "Equation" tab (in the bottom pane of the window), it shows you the equation for how the output relates to the input. In the equation view & means AND, # means OR, $ means XOR, + means addition, and SUM()/CARRY() indicate the sum and carry of an adder block.

Secondly, you will see in the top pane of the window a drawing of the LUT. Underneath that drawing, there are one or more tabs. In the example there are two, the black box view, and a second labelled 'F'. If you go to that tab, you see the full logic breakdown of the LUT.

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