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I'm tryinig to implementan IIR filter like:

y(n) = 2*y(n-1)-y(n-2)+x(n)-2*x(n-6)+x(n-12); 

My vhdl code is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ECGfilter is
    Port (
        reset: in std_logic;
        clk: in std_logic;
        filter_in : in std_logic_vector (0 to 15); 
        filter_out: out std_logic_vector (0 to 23)
    );
end ECGfilter;

architecture FPB of ECGfilter is
    constant size_x : integer := 15;
    constant size_y : integer := 23;
    constant size_bank : integer := 12;
    type input_bank is array (0 to size_bank) of std_logic_vector(0 to size_x);
    type output_bank is array (0 to size_bank) of std_logic_vector(0 to size_y);

    signal x_bancoFPB : input_bank := (others=> (others=>'0'));
    signal y_bancoFPB : output_bank := (others=> (others=>'0'));

begin
    process(reset, clk)
    variable res_aux : std_logic_vector(0 to size_y) := (others =>'0');

    begin

        --Si el reset se pulsa (asíncrono)
        if (reset = '1') then
            x_bancoFPB <= (others=> (others=>'0'));
            y_bancoFPB <= (others=> (others=>'0'));
        elsif (clk'event and clk = '1') then
        --Funcionamiento síncrono.
        --Se actualiza información en los bancos de memoria
            for i in 0 to (size_bank-1) loop
                x_bancoFPB(i) <= x_bancoFPB(i+1);
                y_bancoFPB(i) <= y_bancoFPB(i+1);
            end loop;  

            x_bancoFPB(size_bank) <= filter_in;          

        --Se realiza la aritmética entre posiciones del banco de memoria
          res_aux := (2 *y_bancoFPB(size_bank-1))  - 
                                      (y_bancoFPB(size_bank-2)) + 
                                      (x_bancoFPB(size_bank))   - 
                                 (2* (x_bancoFPB(size_bank-6))) + 
                                      (x_bancoFPB(size_bank-12));


            y_bancoFPB(size_bank) <= res_aux;
            filter_out <= res_aux;

        end if; 
    end process;   

end FPB;

When I try to obtain res_aux, I get the following error (Vivado simulator):

ERROR: [VRFC 10-724] found '0' definitions of operator "*", 
cannot determine exact overloaded matching definition for "*"

It's caused by the 2* multiplication. I know that I have the option of shift 1 bit to obtain the same result. However, I want to know why is this error.

Thanks!

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In VHDL you cannot use arithmetic operators with std_logic_vector.

The problem is that the compiler don't know whether you want to use a signed or unsigned vector.

To avoid this, you can declare your signals as singed/unsigned or just convert them when you want to multiply them using unsigned(your_slv)or signed(your_slv).

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