# Decoupling Capacitor (High Frequency Spike)

Wondering if anyone could help me rectify my understanding of decoupling capacitors and their role in suppressing high frequency voltage spikes (particularly increases in supply voltage).

Similar Question.

The answer provided above does not explain to me the inherit nature as to why a decoupling capacitor will suppress these surges. From my understanding, a capacitor placed at an input pin should shunt excess current through the capacitor proportional to the rate of change of voltage.

If such a transient spike travels down the supply line, shouldn't the voltage seen by the decoupling capacitor and the input pin be identical? The decoupling capacitor serves to shunt current, but the voltage is effectively unchanged. If the incoming transient spike is seen by the node at the capacitor, shouldn't this same voltage be seen by the input pin?

Forgive my confusion, any insight would be great. Thanks.

• It might help you to see it as current travelling around, causing voltages – PlasmaHH May 23 '16 at 11:27

From my understanding, a capacitor placed at an input pin should shunt excess current through the capacitor proportional to the rate of change of voltage.

That is precisely how it works but all supply lines will have inductance and some resistance and this makes the capacitor effective in restricting the rise of the voltage spike. A capacitor on its own has no effect; it is the capacitor in conjunction with series components such as L and R that make it effective against fast transients.

However, for a continuous or long term change the capacitor is ineffective.

• Would you possibly be able to elaborate on how the introduction of the decoupling cap works in conjunction with the parasitic inductance and source impedance? I'm having trouble visually how the transient propagates and is isolated locally to the cap and does not appear at the load. – yan May 23 '16 at 11:52
• @yan - I would encourage you to use a sim tool such as LTSpice - you can quickly model all sorts of scenarios but the short answer is with resistance and inductance in series with the voltage source, the potentially fast rise will cause a big current through the capacitor which drops a big voltage across the series components and hence limits the voltage rate of change across the capacitor. – Andy aka May 23 '16 at 11:58
• Thanks Andy, I actually attempted to model the scenario in LTSpice prior to posting. However, at that point, I was unaware the involvement of parasitics affecting the cap's transient limiting capabilities. – yan May 23 '16 at 12:00
• The parasitics in series with the supply feed ALLOW the capacitor to protect. – Andy aka May 23 '16 at 12:26
• Yes, sorry for the confusion, that is what I was referring to. Having modeled a basic schematic in LTSpice I can see it clearly now. Thank you. – yan May 23 '16 at 12:27

The transient will have some source impedance. Alternatively, you could view the transient as a pulse of energy. Some of that energy will be passed through the capacitor - this acts as a voltage divider with the source impedance so even if you had an ideal bus-bar (supply, decoupling, load) the transient would be reduced. In practice, the supply line has inductance and resistance which also contribute to the isolating effect of the capacitor. None of the real components in a circuit are 'ideal'.

You are right the Vin = Vout for a capacitor in parallel. But in real life a small PCB trace or wire has milli-ohms resistance. These resistances (series resistance at the input and output) contribute a lot in the effect of clamping voltages. the parallel capacitor will look like an RC low pass filter after you add those small resistances.

Note that this means that the PCB layout will have a huge effect on the decoupling effectiveness. This is why you will find dozens of application notes and guides on how to properly place a decoupling capacitors. Also, to increase the effectiveness, many add ferrite beads, inductors or even small resistors in series.