VCC pour and decoupling capacitors on a dual layer board

Question

I am designing a simple dual layer board which has some ICs that I have to put decoupling capacitors near them.

Initially I wanted to make both top and bottom layer as ground plane and route signals and power with traces. But then I found this answer here and decided to make my top layer a power plane (but honestly did not understand why!)

So my question is, should I forget the VCC plane and make both top and bottom planes as ground?

My board has only one 5V supply input called VCC_IN which then goes into a EMI filter (which I am not sure if it is going to be any good) and after R11 (R11 and R12 are going to be 1206 ferrite beads) and C14 it will be called VCC and turns into a power pour.

So, I wonder what kind of effects I am going to see on C1 and C2 as decoupling capacitor compared to if the top pour was also ground and I just routed VCC using a normal track?

The ground plane is ripped off in the image for better visibility of top layer

Answer 1

There are pros and cons.

The advantage of ground on both sides is that you can tie the two ground planes together directly with vias. The advantage ofone side power and the other side ground is that it can provide lower DC voltage drop.

Whatever you do for high speed signals you need to think about your high frequency return paths. The return path should generally be as close as possible to the signal path to minimise inductance. If part of the return path flows through a power plane and part through a ground plane you can tie them together with a capacitor.

A 2 layer board will always be a compromise for high speed because your planes inevitablly end up quite "cut up".

As far as providing power decoupling for the ICs themselves the general rule is that it should be as close to the IC as practical. Your board seems to have a lot of unnessacery space between the capacitors and the IC.

Answer 2

Keep the Vcc plane over as much ground plane as possible. This creates a board-sized capacitor to keep RF noise to a minimum. But you need vias to connect the gnd layers often, especially near decoupling caps ground side.

You can keep any power traces about .100" wide for a local feed (coming off of the Vcc plane), then slim it down to .020 to .030" up at the smd parts.

Any ground plane on top should only be used to isolate and shield HF / RF signal traces on both sides of the board. No issues for C1 or C2.

The only issue that would change the board layout is if you were using frequencies over 200MHZ, then you would use custom board layout software for routing the traces and gnd and Vcc coverage. In such a case the gnd plane would be in a polygon pattern to break up standing waves

Answer 3

Keep the VCC plane. Keep in mind current travels in loops. What happens is that current travels from the power input to the capacitor, through it and back to the ground connection through the ground plane.

The capacitor acts as open circuit at DC. If you get some high frequency interference, it will go through the capacitor and will not interfere with your power supply. What will happen if you have a track instead of a VCC plane is that the track will introduce higher impedance in series with the capacitor. This will reduce the capacitor's ability to provide low impedance connection to ground filtering the interference.

Another problem is the current loops. Power planes will help you minimize them reducing your emissions.

Answer 4

It is good practice to have power and ground planes, as the post you linked to states that having your layer stack-up in this manner creates a fairly nice bypass capacitor in the fab, and can reduce EMC/noise/common-mode and differential mode emissions from the PCB.

I would keep your VCC plane, and try to place the decoupling capacitors as close to their pins on IC1 as you can. Keep the traces as short as possible to IC1 and your power/ground planes. If there is any ripple/noise on your power, these capacitors will ensure your power to the IC remains smooth and stable.