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I am doing research in asynchronous circuits. I got to this section of "Asynchronous Circuit Design A Tutorial" by Jens Sparso which explains handshaking protocols.

There are four protocols discussed:

  1. 4-phase bundled-data (single-rail)
  2. 2-phase bundled-data (single-rail)
  3. 4-phase dual-rail
  4. 2-phase dual-rail

I understand all the first three protocols fully. I only struggle to understand the "2-phase dual-rail" protocol.

In the textbook there is a figure which explain how this "2-phase dual-rail" work for two bits data pack (each bit is represented with two wires):

Illustration of the handshaking on a 2-phase dual-rail channel.

What I don't understand is how those "00", "01", "00", and "11" are inferred from the signals.

The proper tags are "asynchronous circuits", "handshake protocols". But I could not find those tags, so I set it to more general tags, like "circuit-design".

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2 Answers 2

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It seems pretty clear that a transition on the XXX.f rail indicates that the next bit is a zero, while a transition on the XXX.t rail indicates that the next bit is a one.

The ACK rail toggles whenever one transition has been seen on each of the input pairs.

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  • \$\begingroup\$ It was really not clear, and the author didn't explain in his textbook. But now it is crystal clear. Thanks Dave. \$\endgroup\$ Commented May 24, 2016 at 17:07
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The first thing that you need to know is that the difference between 2-phase and 4-phase architectures are that the 2-phase is just a toggle control version of the 4-phase. Sutherland's work got a Turing Award from the ACM in 1988, and his work is floating around on the web.

Async work is very circuit driven: you have an XOR that tells you when you've completed because you do not know when the signal will arrive. You use this XOR to drive the completion tree after you arrive at your Flip-Flops. What this means is that everything is dual rail encoded everywhere. The XOR output sets the complete flag.

The timing diagram that you have is really pretty terrible because it's assuming some added delay, which exists, but is conceptually hard to grasp. As an example, the ACK line should go high right after d0.f goes high because at that point, both d1.t, d1.f are compliments and d0.t, d0.f are compliments, so the XOR outputs from the lines should be 1. The signals are complete and the ACK should happen at that point.

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