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How can I know with which flip-flop I can design a complex logic circuit with minimum number of logic gates?

In our homework and exams, we are supposed to use minimum number of logic gates. In one problem, we are asked for designing a register with simple binary counter, serial load, 2 bit rotation, and parallel load options(synchronization is not mentioned in problem). We are free to use whatever flip-flop we want to use. Which flip-flop would you use in this case? And why? Is there a way to know with which flip-flop we could design the logic circuit with minimum number of logic gates?

Thanks in advance.

Edit: In this assignment, we're allowed to use D, T, SR, JK flip-flops. The problem is, when we use different flip-flops, our combinational part of the circuit is different, is there a way to know with which flip-flop this part would be smaller(contains less number of logic gates).

The register we are asked to design is holding 4 bits. We have 2 bit input which specifies the operation will be running on register(counting, rotating, parallel loading, serial loading).

And by "rotation", I mean Circular Shift

Also, nothing mentioned about "synchronization", so I think it's up to us.

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Serial/parallel-load shift registers and bit rotations are going to work most naturally with a D flip flop, since they just send data straight through; binary counters are going to work most naturally with a T flip flop, since each counter bit Ck = Ck,previous XOR carryk, where carry is the carry bit from the previous stage.

If you look at JK flip-flops, however, they are the "universal" flip-flop that can act as a D- or T- flip-flop depending on the input signals.

To get a D from a T, or vice versa, you need an XOR gate. To get a T from a JK, you just tie the JK inputs together. To get a D from a JK, you need an inverter, as the J/K inputs need to be opposites.

In your application, you've got enough complexity, that I suspect the gate counts are going to be very close, and it's probably not worth worrying about -- unless you have to optimize, in which case you'll just have to try it for each case.

IMHO, the D flip-flop is conceptually the simplest to use, and it works naturally with most of your operations, so I'd start with that.

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The latching arrangement which can be realized using the smallest number of gates (for the latch itself) is the RS latch (commonly realized as two NAND gates, two NOR gates, or a NAND and a NOR). This circuit will switch one way when one input goes active, and switch the other way when the other input goes active. No other latch is simpler, but generating the two separate inputs required by the RS latch may require more outside logic than would be needed with other latching circuits.

Additionally, when building latches out of gates, it's often necessary to make assumptions about propagation delays--in particular, the ratio between the minimum and maximum propagation gate times. Many latching circuits have inherent race conditions which would fail if a signal were to propagate through e.g. one sequence of five gates faster than it propagated through some other sequence of three. In reality, it's possible to bias a few particular gates so as to guarantee that they will be slower than others, but what are you allowed to do here? Conceptually, I like the notion of designing circuits with two clock inputs, which require that the clocks switch in a particular sequence but which will be totally free of internal race conditions provided the clocks are sequenced correctly. Given such a circuit, if one builds a clock sequencer whose time between output clocks exceeds the maximum propagation delay in the downstream circuitry, ensuring that the proper signals will "win" a race condition in the clock sequencer will ensure there are no other "surprise" race conditions in the design.

If one is allowed to regard latching devices as 'primitive components', the most versatile one is the JK flip flop; a T flip flop is essentially a JK flip flop with the two inputs tied together. Counting is often slightly easier with a T flip flop than a D flip flop, but loading and shifting operations are easier with a D flip flop; reasoning about the overall circuit may be easier with a D flip flop than the other types, so that's what I'd suggest starting with.

Conceptually, I would suggest figuring out what each bit is supposed to do in relation to the various states. There are two approaches I'd suggest trying:

  1. Regard a "shift" as being similar to a "count", except that (1) each bit's "carry out" will reflect the state of the bit, without rather than being the bit value "anded" with the "carry in", and (2) each bit's "new value" will simply be the carry in, rather than being the carry in xor'ed with the old value.
  2. Use a mux to distinguish "count" modes from "load" modes, and then use another mux to distinguish "load with old value shifted one bit" from "load with value on parallel input".

I would expect the first approach would probably yield slightly less circuitry. Note that in either case, "circular rotate" sounds the same as "serial-load", except that a mux feeds the most significant bit back to the shift/carry input.

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  • \$\begingroup\$ thanks for your answer. I updated the question to clarify more \$\endgroup\$ – sinan Dec 13 '11 at 17:05

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