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G'day All, Is there a method comparable to jtag debugging on a microcontroller (ATMEGA32) for the Cyclone IV family of FPGA? I am trying to debug my Verilog code so ideally I just want to be able to step through cycles and be able to read the value of a particular "register"(Not the correct term I am sure). I have looked at the docs and they describe many different options like "system console" and RTL etc and I have heard of "test benches" but not really got my head around how they work. I'm not expecting any help with the Verilog code (yet....) just confused about what (if any) option should I be investigating.

Thx Ben.

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Simulation is what you want - read up on how to make a simple testbench for your circuit (apply clock and reset). Tie low any inputs which can be ignored for the simple cases, work up to having a matching machine in the testbench side of the simulation to at least exersise (if not check) your design.
Starting with trying to debug an FPGA is a waste of time, unless you're really confident (and then its a close call).

Simulation gives you a view of all the internal nodes (wires or flops), in either the original HDL you wrote, or the netlist which results after synthesis (here the real timing delays can be used, but generally you want to avoid that)

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  • \$\begingroup\$ Thanks Sean. I will definitely look at a test bench now. \$\endgroup\$ – BenG May 24 '16 at 22:52
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You can't easily "single step" an FPGA design, unless that capability is part of the design itself. But Altera offers an embedded logic analyzer called SignalTap that you can use to probe signals in real time.

But it's usually better to do the bulk of your debugging in the simulator; the visibility into what's going on and the ability to change things on the fly is so much better.

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