I have two flips flops as so. The clocks are connected, even though it is not shown in the picture.
Given this image, I am trying to figure whether the contamination delay or the propagation delay of flip flop 1 would cause a hold time violation of flip flop 2. The correct answer is contamination delay but I am having trouble understanding why.
What I know is: the setup time and hold time are related to the input, contamination/propagation delays are related to the output.
Looking at it more in depth, setup time is the time before the clock edge that the input D must be stable and hold time is the time after the clock edge that the input must be stable.
Similarly, contamination delay is the time after the clock edge that the output might be unstable (i.e. starts to change). Propagation delay is the time after the clock edge that the output is guaranteed to be stable.
Given this knowledge, I am not sure why the contamination delay would cause a hold time violation. If the output changes instantaneously, let's say, before the clock edge (i.e. the contamination delay = 0), then why would that affect the hold time of flip flop2? A comprehensive explanation of this would be very helpful.
