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I have two flips flops as so. The clocks are connected, even though it is not shown in the picture. enter image description here Given this image, I am trying to figure whether the contamination delay or the propagation delay of flip flop 1 would cause a hold time violation of flip flop 2. The correct answer is contamination delay but I am having trouble understanding why.

What I know is: the setup time and hold time are related to the input, contamination/propagation delays are related to the output.

Looking at it more in depth, setup time is the time before the clock edge that the input D must be stable and hold time is the time after the clock edge that the input must be stable.

Similarly, contamination delay is the time after the clock edge that the output might be unstable (i.e. starts to change). Propagation delay is the time after the clock edge that the output is guaranteed to be stable.

Given this knowledge, I am not sure why the contamination delay would cause a hold time violation. If the output changes instantaneously, let's say, before the clock edge (i.e. the contamination delay = 0), then why would that affect the hold time of flip flop2? A comprehensive explanation of this would be very helpful.

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  • \$\begingroup\$ Unless you are living in a non-causal world, the output cannot change before the clock edge, so please explain your contamination delay again. Plus, without knowing the relative timing of the two clock inputs, there is no way to talk about the sequential behavior. \$\endgroup\$
    – WhatRoughBeast
    May 24, 2016 at 22:44
  • \$\begingroup\$ Opps, sorry about the definition. fixed. And what do you mean by the relative timing? \$\endgroup\$
    – Jonathan
    May 24, 2016 at 22:47
  • \$\begingroup\$ Your two clocks are not tied together. Therefore, there is no way to tell what the relative timing of the clocks is. For instance, if the FF has a 5 nsec max propagation delay, and you run the clock to the second FF 10 nsec after the first, there is no problem. \$\endgroup\$
    – WhatRoughBeast
    May 24, 2016 at 22:53
  • \$\begingroup\$ I see. I have added in the related detail in the question. Thank you. \$\endgroup\$
    – Jonathan
    May 24, 2016 at 22:58

1 Answer 1

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The hold time is the time the input must be stable after the clock edge for the data to be sampled correctly by the clock edge. In many cases it is zero, but let's say it is 2 nsec. If your contamination time is 1nsec, it means that after 1nsec the output of the previous FF (input of the next one) started to chage => hold time of the second FF was violated

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    \$\begingroup\$ If the first FF input/output is metastable, and both flip-flops share the same clock, the output of the second FF is stable, but unknown, as a metastable error propagates until a digital filter removes it. Contamination can create metastable states with unknown results. \$\endgroup\$
    – user105652
    May 25, 2016 at 0:04

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