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Peripherals in Micro-controllers usually provide a way for us to send and receive data from it. Usually this are memory mapped registers.

I have come across few terminologies. The most often used one is a buffer and probably a FIFO. But when working with CAN controllers, I came across Mailboxes.

Now I am confused.

What is the difference between a buffer and a mailbox. Or a FIFO and a mailbox.

Thanks!

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  • \$\begingroup\$ i guess u might have come across mailbox in a TI uC? \$\endgroup\$
    – AlphaGoku
    May 25, 2016 at 10:27
  • \$\begingroup\$ All CAN controllers usually have mailboxes. \$\endgroup\$ May 25, 2016 at 11:29
  • \$\begingroup\$ NXP LPC series dont. They have Receive buffers \$\endgroup\$
    – AlphaGoku
    May 25, 2016 at 11:36
  • \$\begingroup\$ Oh. Rx can be done with FIFOs but Tx usually needs Mailbox because you would usually expect messages with higher priority ID to be sent out first and hence you can't have a FiFO and CAN controller needs a way to check which item has highest priority. \$\endgroup\$ May 25, 2016 at 11:38
  • \$\begingroup\$ Even Tx can be done using only buffers(NXP LPC uses no TX mailboxes).You can however set priority among 3 Tx Buffers. \$\endgroup\$
    – AlphaGoku
    May 25, 2016 at 11:41

2 Answers 2

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A buffer is simply a collection of data registers that your program can access. In case of CAN, there is usually one or several "control field registers" where you can find the CAN identifier, message data length, RTR and such things. Followed by 8 bytes of the actual data.

A FIFO (first in first out) is simply a number of buffers, that form a queue. The first item to arrive in the queue is the first to leave. This is handled by hardware, so that you don't have to trigger an interrupt to service each and every CAN message. Most commonly there will be a Rx FIFO for received messages - this makes most sense since these would be causing interrupts, but some CAN controllers also support some manner of Tx FIFO.

In the case of Tx FIFO, it is usually just a mechanism to allow you have several out-going messages (usually 3), but have the CAN controller pick the one with lowest CAN identifier at the next point of message arbitration on the bus. There are also plenty of dumb CAN controllers which requires you to set a manual "Tx prio" instead of simply using the CAN identifier. Avoid these.

It is possible that some microcontrollers support DMA for CAN buffers, so that you can have them stored directly in some convenient chunk of RAM, instead of having to repeatedly poll/interrupt trigger on the CAN peripheral's registers.

Mailboxes is a different alternative. Each mailbox is a buffer (rx and/or tx), but it can be configured to only work with one specific CAN identifier. Meaning that it also have a receive flag and maybe also interrupt possibilities. These are perfect for systems where your MCU is only interested in a limited amounts of identifiers.

One more advanced, but fairly common setup, is to combine a Rx FIFO with mailboxes, so that high priority messages will end up in their dedicated mailbox, while everything else ends up in the FIFO. This could be a good solution for more advanced CAN applications like for example CANopen, where you have countless possible identifiers on the same bus.

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  • \$\begingroup\$ Thanks. That was clear. Do you know any other peripheral that uses Mailbox feature/terminology for buffers other than CAN? \$\endgroup\$ May 25, 2016 at 14:25
  • \$\begingroup\$ @RaviTejaGudapati I can't really think of one, CAN is a bit unique when it comes to data communication, since it uses identifiers instead of destination addresses. I suppose various CAN offspring like FlexRay or LIN might use mailboxes too. \$\endgroup\$
    – Lundin
    May 25, 2016 at 14:34
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A buffer is a fairly generic term, so you will have to rely on context to determine specifics, a buffer is used to temporarily store data before it can be processed e.g. buffering data before it can be transmitted.

FIFO is an acronym for First In, First Out; it describes how the order of incoming items corresponds to the order of outgoing items; for example the data structure that implementers FIFO ordering is the queue. Often FIFO is used as an adjective, e.g. a FIFO buffer is a buffer that can store multiple items and outputs them in the same order as recieved. The simplest hardware example of a FIFO buffer would probably be a shift register.

The term mailbox implies some sorry of addressing scheme is in use i.e. each mailbox had a unique identifier or address. Specifically in the CAN standard (a communication standard), conceptually a mailbox is an addressed buffer, essentially the CAN control checks the ID specified in a message and if it matches the mailbox the message contents are stored in it.

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  • \$\begingroup\$ Thanks. Also, if it is a FIFO buffer in peripheral, is it possible to address individual item in the FIFO. I am guessing not. My guess is FIFO is usually abstracted away from the user and the head of the buffer is exposed in the memory mapped registers. So you know multiple messages/data can be queued but it is totally managed by the peripheral. Is this right? \$\endgroup\$ May 25, 2016 at 11:28
  • \$\begingroup\$ @RaviTejaGudapati That depends on the CAN controller. Some controllers do have this possibility, some don't. For example Freescale FlexCAN controllers have mailboxes, but you can sacrifice x number of them to use as a rx FIFO. In that case it is possible to access any item in the FIFO regardless of when it arrived (not quite sure why you'd ever want to do that though). On other controllers you are only able to read the oldest FIFO message, and when that is read from the rx buffer, the controller will shift in the next message. \$\endgroup\$
    – Lundin
    May 25, 2016 at 13:23

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