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In Altium Designer, I'm using Keep-out layer lines to enforce the manufacturer's board-edge clearance restrictions. The problem is, that the top layer polygon will pour around these lines, which is not necessary.

How can I make the polygon pour act like the keep-out layer was a silk-screen layer, i.e. just ignore it.

If I set the clearance rule to 0 or matching "NOT OnLayer('Keep-Out Layer') ", it will have no clearance but still have no copper directly below the line.

Polygon pouring around the keep-out layer lines

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  • \$\begingroup\$ When pouring the polygon, check the box labeled something like "remove unconnected copper". \$\endgroup\$ – brhans May 25 '16 at 19:18
  • \$\begingroup\$ @brhans this will remove the bit of copper at the pcb edge, ok better but still not the way I'd like it to be! \$\endgroup\$ – Xaser May 25 '16 at 19:24
  • \$\begingroup\$ Aah ok - maybe along with 0 clearance you could also set a 0 line width ... My Altium allows that. \$\endgroup\$ – brhans May 25 '16 at 19:30
  • \$\begingroup\$ @brhans yeah I thought about that, but that workaround is on the level of deleting the keepout layer when generating the gerber files \$\endgroup\$ – Xaser May 25 '16 at 19:39
  • \$\begingroup\$ Remove the DRC rule that says polygons can't touch keepout objects. Or rather edit the rule that says "anything touching a keepout is a violation" to say "anything except a polygon touching a keepout is a violation". \$\endgroup\$ – The Photon May 25 '16 at 20:25
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Personally, I like Derstrom's answer for its simplicity about using Altium's built-in solution. However, if you need keepout clearances not on your board edge, it won't help you there.

What I do is create a rule for my clearance on my outer layers, called say BoardOuterLayer_Clearance:

enter image description here

Then I create a similar rule called BoardInnerLayer_Clearance, make it lower in priority, to catch the other layers, and this second rule is exactly the same as the first except second object matches "All."

This lets me set the pullback for inner layers to something higher, say, 15mils, since often the board houses recommend this.

Then I just need draw a boundary around my board and any pours or online routing rules will respect this. Here you can actually see I put my KOR already pulled back at the inset, so a bit of overkill here on this board. But in this image, the polygon pour goes all the way to the board edge, so the pour is respecting the rule:

enter image description here

Of course, the real beauty of this method is that it will work everywhere. So here I have a footprint for a screw hole, with silkscreen to indicate to the designer but there is also a circle drawn in keepout layer there that will keep any screw heads from eating through and biting into copper.

The rule handles this for me and all I have to do is draw keepout wherever I need it once I've set up the rule.

enter image description here

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  • \$\begingroup\$ very good solution, I think I will modify this rule to ignore polygons so they can go to the very board edge. \$\endgroup\$ – Xaser May 26 '16 at 16:45
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    \$\begingroup\$ @Xaser I think I misunderstood your intent, but after reading your comment, I see you want the poly to ignore the rule. You could do this by getting fancy with the queries in Altium, but my absolute recommendation is you do not do this. It is best practices to pull back planes from the edge as well, because in a system the sides could short against a chassis. Do not worry about the manufacturers tools being unable to etch at edges. They'll either panelize your board or route out out a single board from a bigger panel. Either way there will be excess to etch around. \$\endgroup\$ – Joel Wigton May 26 '16 at 16:59
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Personally, I use the built-in Board Outline Clearance rule located within the "Manufacturing" category:

enter image description here

This should produce a DRC error if components or traces are placed too close to the outline (if it lets you place them too close in the first place), and will also prevent polygon pours from pouring too close or outside of the outline.

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  • \$\begingroup\$ this solution is very nice, however will this not cause the manufacturer to etch the copper away from the edge (where possibly the tools do not work well?). Why would I not want the polygon copper to go to the very board edge? \$\endgroup\$ – Xaser May 26 '16 at 16:44
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    \$\begingroup\$ Boards are generally manufactured in panels, so the copper is etched before the boards are cut. Pulling copper all the way to the edge of the board presents the risk of the layers shorting at the edges when the boards are cut. It's best practice to keep the copper pulled back from the expected board edge by at least 15 mil (roughly 0.4mm) to prevent this sort of problem. I have also heard of people who had the copper poured all the way to the edge of the PCB, and they received a shock when holding the board on the edges during use. This could mean that it might short to its enclosure as well \$\endgroup\$ – DerStrom8 May 26 '16 at 17:17
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DerStrom8's and Joel's solutions do not work for older versions of Altium.

The easiest solution is adding a new constraint for the clearance definition. To make the keep out layer solid ground, define the following constraint. "All And Not IsKeepOut"

enter image description here

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