I am working on a Mixed signal model where the symbol looks like the following, enter image description here

The signal to the left is count_val which is std_logic_vector(7 downto 0) and p,m are the terminals which have qunatities voltage v and current I.

Its a very simple code where we have to use the count_val to calculate the current i. In simple terms it should be like this, I == 0.00003 * count_val.

But since count val is std_logic_vector and I is a "quantity" which is analog this makes the above formula hard to implement. I tried to convert the count_val to an integer type and use it in the forumla but still no luck and the forumula 'I == ' accepts only quantities in it and not signals or std_logics . Is there a way to crack this issue ?

The overal block diagram looks like this and at the bottom where the contolable current sink is, is where I am stuck as I am not able to controll the current sink with the counter due to the above mentioned reasons.

enter image description here


If you draw a new schematic with the built-in editor it would be easier to see what is going on.

How will the counter control the voltage and current? It sounds like you will need a DAC and an amplifier if you were to really build it.

I have to force myself to think about real systems when I'm designing with VHDL. It's not like a HLL such as Java or C++. Those languages try to be as far away from the hardware as possible.

VHDL, however, models real circuits since it is used for synthesis and P&R on an FPGA.

Here are some type-casting examples showing how to change a std_logic_vector into a signed or unsigned int (page 9).

Here's an intro for VHDL-AMS I found from a Google search.

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  • \$\begingroup\$ Hey thanks for your reply, now I have added another block diagram..May be I do need a DAC but I am not sure. And the casting type examples that you gave I hae already tried but the problem is a "qunatity" accepts only constants or another quantity in its equation. So I have to find a way to make the conter values into a quantity (DAC) prior to using it ! This seems to be the only option I guess. \$\endgroup\$ – Bhuvanesh Narayanan May 27 '16 at 8:12

I found the answer now, While using VHDL-AMS if you have to perform an assignment operation with a quantity for example

let I be the quantity flowing throught the terminal from p to m then,

I == 0.0003* Isc ; --where Isc is also another quantity

This would be possible easily but when you have to use count which is a std_logic_vector(7 downto 0) for the same operation instead of Isc, for example

I == 0.0003*count; --This is wrong because you cant assign a std_logic toa quantity.

So first convert the std_logic_vector count to an integer

cnt_integer <= CONV_INTEGER((count));--Convert first

Then use real to include this integer into your forumla,

I == 0.0003*real((cnt_integer)); --This works !!

So this real((x)) is important which I missed earlier.

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