I've designed various transconductance and operational amplifiers in CMOS technologies in the past. I've also worked with clocked latching comparators. However, I've yet to design an asynchronous comparator, and its internal design seems strongly similar to an op-amp.
Suppose I wanted to design a comparator with a fully driven output (not an open drain). How would the design of my comparator and the factors I take into consideration differ, at an integrated transistor level, from a one- or two-stage opamp optimized for linear negative-feedback operation? Changes in topologies, biasing, sizing strategy?
To start off, I would suppose that you'd want a different second stage topology capable of high slew rate rail-to-rail output (and disregard its small-signal operation)... perhaps also node charge/capacitance considerations for fast recovery of the first stage from saturation?
Please note that my interest is at a transistor circuit level for integrated technologies, not at a board level. I am aware of question 90657, which covers this at an abstract/black-box level, and did not find any questions that cover this topic at an IC level.