I've designed various transconductance and operational amplifiers in CMOS technologies in the past. I've also worked with clocked latching comparators. However, I've yet to design an asynchronous comparator, and its internal design seems strongly similar to an op-amp.

Suppose I wanted to design a comparator with a fully driven output (not an open drain). How would the design of my comparator and the factors I take into consideration differ, at an integrated transistor level, from a one- or two-stage opamp optimized for linear negative-feedback operation? Changes in topologies, biasing, sizing strategy?

To start off, I would suppose that you'd want a different second stage topology capable of high slew rate rail-to-rail output (and disregard its small-signal operation)... perhaps also node charge/capacitance considerations for fast recovery of the first stage from saturation?

Please note that my interest is at a transistor circuit level for integrated technologies, not at a board level. I am aware of question 90657, which covers this at an abstract/black-box level, and did not find any questions that cover this topic at an IC level.

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    \$\begingroup\$ I think you pretty much hit the spot: a high-speed opamp design will make a fine comparator; not needing the constant gain, however, makes your second stage easier. Go for higher base currents. \$\endgroup\$ May 26, 2016 at 23:34
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    \$\begingroup\$ In CMOS, I use the folded cascode architecture for the opamp, and for the comparator, I use the classic push-pull, but you don't need that compensation capacitor between stages because you are trying to rail the thing. \$\endgroup\$
    – b degnan
    May 26, 2016 at 23:38

2 Answers 2


You'd leave out the compensation capacitor etc. and you have to make sure your front end topology will tolerate high differential voltage (many op-amps cannot - they may have something like back-to-back diodes across the input with some series resistance).

Also, for many applications, offset voltage and gain is not as importance as speed, so those parameters are compromised for the sake of speed.

  • \$\begingroup\$ Accepting this answer because it's a better overview of various design goals, though the other answer here is also useful and touches on stability/compensation slightly more. (Also, yes, several months later—oops!) \$\endgroup\$ Jan 26, 2017 at 11:45

The main difference is that opamps need to be stable when in a negative feedback configuration. This means that they need to be compensated. Compensation slows your slew rate.

For comparators stability is not such a big problem. All you need to ensure is that it saturates and doesn't oscillate.

Comparators also have two output states. This means that gates can be used improving the speed but they introduce parasitics. See this


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