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I've been trying to synthesis this register model. Its simulation in ModelSim is correctly fine. However, when synthesis, it always yields warnings:

[synth 8-3331] design register1 has unconnected port rst

[synth 8-3331] design register1 has unconnected port end_data

Here is the code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity register1 is
    port(
        rst      : in  std_logic;
        end_data : in  std_logic;
        clk      : in  std_logic;
        D        : in  std_logic_vector(7 downto 0);
        Q        : out std_logic_vector(7 downto 0)
    );
end entity register1;

architecture RTL of register1 is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' or end_data = '1' then
                Q <= "UUUUUUUU";
            else
                Q <= D;
            end if;
        end if;
    end process;

end architecture RTL;

I don't know what wrong. Could it be my coding style?

Hope you guys could help me. It's been very irritating.

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6
  • 1
    \$\begingroup\$ How do you expect the synthesizer to assign "uninitialized" as a state to a register? \$\endgroup\$ May 27, 2016 at 4:39
  • \$\begingroup\$ what should I use in stead of "uninitialized"? \$\endgroup\$ May 27, 2016 at 4:48
  • \$\begingroup\$ Choose a valid binary value, consistent with your need. If you don't have a need, why are you providing a reset? \$\endgroup\$ May 27, 2016 at 4:49
  • \$\begingroup\$ I wanna use "uninit" because later when compare output from 2 register, the result will be "not equal". Could you recommend me any other ways to fix this? \$\endgroup\$ May 27, 2016 at 4:57
  • \$\begingroup\$ Add a 'valid' output that is set to '0' in the reset state, and '1'in the other state. Your outer comparison would then look at valid and Q to determine equality. \$\endgroup\$
    – scary_jeff
    May 27, 2016 at 8:37

2 Answers 2

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At the hardware level, nothing is wrong and you can safely ignore those warnings.

Assigning "UUUUUUUU" does nothing in hardware, so it gives the synthesis tool explicit permission to save hardware by doing the cheapest thing possible. As a result, two input signals rst and end_data are unused.

Then the synth tool gives warnings - because unused inputs, like all dead code, is a code smell and points to a possible design problem. So read them - understand them and if they are "false positives" (the reset value doesn't matter) ignore them.

But your comments do reveal a design problem - you wish to distinguish between invalid and valid inputs, which is not generally possible in hardware - a FF can hold '0' or '1' and that's it - no other choices (except 'Z' which is restricted to I/O pins, and perhaps, other roles in ASICs)

So at the hardware level' what you want to do is impossible : even if you could assign "UUUUUUUU" it would be represented by a pattern of '0' and '1' and thus your equality comparator would return True for some specific valid data.

So your choices are limited to finding an in-band value that the register will never be assigned (like -1 for a positive number, as is often seen in C programming), or adding a "Valid" bit as Jeff suggests.


At the conceptual level, the metavalues 'X' 'U' and so on are to allow you to find and correct these problems in simulation.

Therefore by the time you synthesise your design, they have all been resolved, and synthesis has permission to optimise the design and save hardware resources where it can. So, what synth does with these values is essentially undefined, and that is OK.

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In fact, the code gets a little simpler if you add a valid output:

entity register1 is
    port(
        rst      : in  std_logic;
        end_data : in  std_logic;
        clk      : in  std_logic;
        D        : in  std_logic_vector(7 downto 0);
        valid    : out std_logic;
        Q        : out std_logic_vector(7 downto 0)
    );
end entity register1;

architecture RTL of register1 is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            valid <= not (rst or end_data);
            Q <= D;
        end if;
    end process;

end architecture RTL;
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