I don't understand why 0xFFFFFFFF is latched at 5 ns and not the previous value 0x0abcdeff. Because the change of the input signal from 0x0abcdeff to 0xFFFFFFFF is initiated by the rising clock edge at 5 ns. Until this signal change propagates to the register input in my opinion the old value 0x0abcdeff should have been latched.
Doesn't the input signal need to be stable before the clock edge for at least the setup time to be latched correctly?
Would a real circuit with the same signal changes as shown in the simulation latch 0xFFFFFFFF or 0x0abcdeff?
In other words does the simulation describe the waveforms that occur in the hardware?
Am I using the enable signal correctly to make it work in hardware? For example if I want to latch a value at the rising edge at 25 ns, do I have to set the enable signal already at the rising edge at 15 ns and reset it at 35 ns? Because if I set enable at 25 ns the propagation time until it reaches the flip-flops would perhaps prevent them from latching the value correctly.
Here's the verilog code:
module Nbit_register( // inputs clk, enable, d, reset, // outputs q ); parameter N = 32; input clk; input enable; input reset; input [N-1:0] d; output reg [N-1:0] q; always @ (posedge clk or posedge reset) begin if (reset == 1) begin q <= 0; end else if (enable == 1) begin q <= d; end end endmodule
And here's the testbench code:
module tb_register; reg clk; reg reset; reg enable; reg[31:0] d; wire[31:0] q; Nbit_register register ( .clk(clk), .reset(reset), .enable(enable), .d(d), .q(q) ); initial begin clk = 0; reset = 0; enable = 0; d = 32'h11111111; end always #5 clk = !clk; initial begin d = 32'hABCDEFF; #5 enable = 1; d = 32'hFFFFFFFF; #10 enable = 0; d = 32'hAAAAAAAA; end endmodule
Ok, I connected two 32-bit registers in series now as suggested by Sean Houlihane and this is the simulation result: These results make sense to me, but I have one question left. Is it ok to reset the enable already at 25 ns or do I have to wait until the next rising clock edge at 35 ns for it to work in hardware?