I at the moment trying to reverse engineer something i made a long time ago but never understood why it is running so slowly.

I have a Zybo board, with an Zynq 7010s chip ons which has dual cortex-A9 processor and a FPGA tightly compacted together.

On the CPU side i made a game, which for each iteration generate an array of decsribing the pixel value of the game image.

=> first question => this array is pretty large, and i am bit unsure where this variable would be stored?.. I just created a variable that had this value.

Next the game image had to be displayed on vga port, for which i how to transfer the data from the PS to PL side. I used the AXI DMA, and transfered it like this:

void send_data(char c_map, u32 target){
    //xil_printf("\r\nStarting sending data\r\n");

    /* Initialize the XAxiDma device.
    CfgPtr = XAxiDma_LookupConfig(DMA_DEV_ID);
    if (!CfgPtr) {
        xil_printf("No config found for %d\r\n", DMA_DEV_ID);
        //return XST_FAILURE;

    Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr);
    if (Status != XST_SUCCESS) {
        xil_printf("Initialization failed %d\r\n", Status);
        //return XST_FAILURE;

        xil_printf("Device configured as SG mode \r\n");
        //return XST_FAILURE;

    //Value = 0b11110000000000000000000101000000;

    if(c_map == WALL){
        Value = 0b11111111111100000000000000000000;
        //Value = 0b00000100000000000000000000000000;
        Value = Value + target;
    }else if(c_map == BALL){
        //Value = 0b10000000000000000000000000000000;
        Value = 0b00000000111100000000000000000000;
        Value = Value + target;
        Value = 0b00000000000000000000000000000000;
        Value = Value + target;

    for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
        TxBufferPtr[Index] = Value;

    Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN);

    Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) TxBufferPtr,

    if (Status != XST_SUCCESS) {
        xil_printf("No XST_SUCCESS \r\n");
        //return XST_FAILURE;

    while (XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE)) {} //wait

In the PL i create a block ram as such

type RAM is array (0 to ADDR_WIDTH+1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal mem : RAM := (others => (others => '1'));

Which supposedly should be a block ram, and then inside my VGA driver fill in my memeory block with the data received as input from the zynq as such.

   if (rising_edge(clk)) then
        if ((hSyncCounter > hBackPorch) and (hSyncCounter <= hBackPorch+hDataLen)) then
            mem(conv_integer(data(19 downto 0))) <= data(31 downto 20);--"111100000000";
       end if;
   end if;
end process; 

Data being an input signal. 31 downto 20 consist of the RGB value of the pixel. and 19 downto 0 is the adress of i gave from the C.

19 downto 0 is just the grid position in the image and not a specific ram location or something like that, but where is the mem I create in the PL stored, or made of? Is it just a big giant mux?


You should be able to use your design tools to check what the synthesizer has done with mem.

Check the RTL schematic first, and make sure it looks 'sane' (i.e. make sure mem appears as some form of RAM). The RTL schematic shows you the non-architecture specific synthesized HDL.

Then check the "Technology Schematic" (I think that's what Xilinx calls it, at least in ISE), which shows you what the optimization/architecture specific synthesis has done with your design. This should show a mem mapped to block RAM(s), or explain what the synthesizer has decided to do with your construct.

| improve this answer | |
  • \$\begingroup\$ So.. It appears to me that mem has become a one giant mux.. Is it possible to see how much logic it uses.. ? \$\endgroup\$ – Sorrow May 30 '16 at 7:58

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