Saturation in differential pair

I'm reading Analysis and Design of Analog Integrated Circuits by Gray & Meyer. In the differential pairs' chapter, there is this circuit

and it says:

Assume the collector resistors are small enough that the transistors do not operate in saturation if $V_{i1} \leq V_{CC}$ and $V_{i2} \leq V_{CC}$.

I don't understand why large values of $R_C$ would lead to saturation for input voltages that are less than $V_{CC}$. Any ideas?

Maybe 'saturation' is not the proper description of what happens. By increasing the values of Rc eventually you will starve the transistors of any useful current, such that Vo1 and Vo2 can no longer rise above -Vee volts (or not by any useful amount). In fact they would approach -Vee the closer to 'saturation' they get.

Lowering Vcc simply compounds the problem by reducing the source voltage to work with. In this case 'saturation' does not mean an overload of the transistors as much as it is about robbing them of the current they need to work properly.

Like having a kink in your garden hose chokes off the water coming out of the hose, and adjusting the nosel does not give you more water until the kink is removed.

Though no values are given, it is assumed that if Vcc is at full voltage and Rc and Rtail at at usable values then Vo1 and Vo2 should be able to swing at least 1/2 of the supply voltage from Vcc to -Vee, or be close to zero volts under 'idle' conditions.

This would make the statement "Assume the collector resistors are small enough that the transistors do not operate in saturation if Vi1 ≤ VCC and Vi2 ≤ VCC" hold true.

• I'm not sure I get what you say. If we increase Rc, then Vc is going to be 0 eventually. Let's assume that the saturation voltage of Vce is 0.2 V. Then, whenever Ve < -0.2 V, nothing saturates. So if Vi - Vbe = Ve < -0.2 V, I don't see the problem. This means that nothing saturates if Vi < 0.5 V (approx.), and there is nothing related to Vcc there. Where am I making the mistake in my reasoning? May 29, 2016 at 22:55
• Your forgetting that the most negative voltage is -Vee. Unless there is sufficient bias current through Rc then Vo1 and Vo2 are pulled down closer to -Vee as long as Vi1 and Vi2 are >.65 volts above -Vee. It is a play on words but one could say that Q1 and Q2 are saturated under such conditions.
– user105652
May 29, 2016 at 23:03
• If Vi1 = Vi2 = -Vee then Q1 and Q2 are forced 'OFF' and Vo1 and Vo2 are dominated by the Vcc/Rc values.
– user105652
May 29, 2016 at 23:06
• I wish you had real parts to work with (and a DVM), then you could see how this all plays out.
– user105652
May 29, 2016 at 23:08
• But what if -Vee < Vi < 0.5 V? Then they would not be saturated and Vi is under Vcc (with Rc being infinite). But this contradicts what the book says! I don't get it May 29, 2016 at 23:10

The problem with the term saturation is that it means different things for bipolar and MOS transistors.

For a MOS diffpair the transistors should work in saturation because then they act like voltage controlled current sources. The drain-source voltage has to be higher than the saturation voltage.

For a bipolar diffpair the transistor should operate in forward-active mode, which means that the base-collector diode is reverse biased. The resulting field will remove carriers from the base and the transistor works as an amplifier. If the base-collector diode becomes forward biased the transistor saturates, which is an undesired condition.

Looking at the base-collector diode we see that two things can drive the transistor into saturation. Increasing the base voltage too much or decreasing the collector voltage too much.

If the resistors RC are too big then it is possible that the voltage drop across them is sufficiently high to push the collector voltage low enough to drive the transistor into saturation.

Therefore it is required to pick a proper value for the RCs.