# Level shifting in HV CMOS processes

I'm working on a project for which custom ICs are being designed by another person on the project. The process being used is a mixed voltage CMOS process which uses a $1.8\mathrm{V}/5\mathrm{V}$ logic level along with a $60\mathrm{V}$ high voltage capability. Essentially the circuits being designed involve high voltage output drivers which must be driven from the low voltage logic. Naturally this requires level shifting.

The high voltage transistors in the process are designed for $60\mathrm{V}$, but as with most transistors, this is only the $V_{ds}$ rating. The $V_{gs}$ rating is naturally much lower - in this case only $5\mathrm{V}$.

The restricted gate voltage clearly makes level shifting difficult - somehow a $5\mathrm{V}$ control signal for the low side needs to be shifted up by $55\mathrm{V}$ in order to control the high side transistor of a half-bridge. However this is not a simple task as the gate voltages are limited.

The IC guys who are working on this basically have two solutions. Firstly, use a resistor for the high side rather than a PMOS which as you can imagine would consume an awful lot of power as the resistance needs to be low enough to achieve fast rise times ($20\mathrm{ns}$) into a fairly large ($10\mathrm{pF}$) capacitive load. Secondly, use a resistive divider driven by a low side NMOS to produce the $60\mathrm{V}/55\mathrm{V}$ logic level for a high side PMOS - but again this would use a lot of power as the gate of the PMOS is a ~$2\mathrm{pF}$.

Not being an IC designer myself, I'm leaving them to do their job, but I suppose it's just been bugging me. I can't help pondering over the problem and thinking there must be a better way, but I can't think of one.

I'm curious as to whether there are typical ways of achieving this sort of level shifting with limited components?

Effectively the only components are the PMOS/NMOS above, resistors, diodes, and I think 5.5V Zener diodes too. There are capacitors in the process to but as I recall they are low voltage, so couldn't be used in structures I've seen that can level shift pulses over a large voltage using capacitors for isolation.

I suppose what is bugging me the most is it seems odd that IC fabs offer high voltage processes with seemingly no 'nice' way of linking the PMOS and NMOS transistor together to form push-pull drivers.

• This may be very inapplicable in the context but may be useful: Easier to draw it if the following word picture is hard to follow (see end for "diagram". | Low side NMOS driver is driven as a follower with Rlow in source. NMOS drain drives high side with a Resistor Rhi to 60V. Voltage across Rlow is Vgate_NMOS - Vgs_NMOS needed to maintain current in Rhi. Maximum voltage on Rhi wrt 60V is V_Rlow_max x Rhi/Rlo. If say Rhi = Rlo and Vdrive is 5V then max voltage across Rhi is 5V and will in fact be less due to Vgs_NMOS > 0 when circuit stabilises. – Russell McMahon Feb 5 '17 at 10:58
• Cct diagram :-) : +60V - Rhi - NMOS drain - NMOS source - Rlow - ground. PMOS gate connects to Rhi bottom end. – Russell McMahon Feb 5 '17 at 10:59

Most technologies are limited to VGS < 10 V, or 5 V in more modern ones, and need circuits like this. High voltage level shifters are needed in high voltage DC/DC converters and similar circuits.

The general approach is to create a rail that is ~ 5 V below the HV supply and use this to limit the VGS of the high side FETs. You also don't drive the 10 pF load directly -- buffers (also powered from the HV-5 supply) minimize the load on the level shifter portion itself.

Care needs to one taken in these circuits to ensure that the HV devices don't get damaged; that the outputs are controlled when the supplies are starting up, and that speed is maintained.

• That makes some sense - I did see reference in the technology specs about floating transistors on a high voltage rail. Presumably it still requires some form of resistor/transistor arrangement to get the control signal up there? but I suppose the resistance can be made larger as the floating buffer would have a lower gate capacitance than the high voltage PMOS. – Tom Carpenter May 30 '16 at 15:48
• I'm going to mark this as the answer. Indeed it will reduce the switching currents significantly as I'm told by the IC guys that the 5V transistor gates (which would be used in the floating buffer) are barely 50 femto-farads so much larger resistances can be used. – Tom Carpenter Jun 2 '16 at 3:36

The usual technique is to use a cross-coupled level shifter. If you use "your favourite search engine" you gets scads of images. This one is grabbed from Freescale

Although you will notice that the PMOS here has gates that are subjected to the full voltage swing.

Having done this before I am wondering if your statement about Vgs is true.

This might be true for a DMOS transistor in an isolated NWell (for the high voltage) but there should be gates that can handle the high Vgs with out oxide rupture.

Any HV voltage devices I've worked with or developed in the past had thicker oxide and could handle the higher voltages.

There are versions of the circuit that cascodes the PMOS and thus reduces the larger voltage swing.

Here is a picture from USPTO application that touches on this a bit. From application US20100201427 A1, although these circuits existed well before the 2010 time frame. Note that cascode transistors 34 & 35 limit the swing of the gate voltages on the high voltage transistors. So this will work.

To limit the voltage swing further would require two external bias voltages and the addition of another cascode like transistor pair. Again from the same patent application and again something that is prior art.

Note that VBiasH and VbiasL will limit the gate excursion on the transistors 26 and 27.

There really is no reason to be using resistors here though. Bad for power, bad for area consumption and very bad for matching.

• I'm aware of the cross-coupled level shifters, but the $V_{gs}$ for all of the transistors in the process is indeed only $5\mathrm{V}$ so those circuits would unfortunately fry the gate oxide. – Tom Carpenter May 30 '16 at 3:47
• @TomCarpenter cleaned up the reply. I was wrong about the first picture, explanation updated. and the extended. – placeholder May 30 '16 at 4:18