I want to implement a counter which can save values through power cycles, so I should use flash memory(I have option to choose NOR or NAND) but as my counter values will be increased frequently. I want to optimize number of erases(considering only erases i.e making bits 0 to 1 will effect the flash life span).

For that I want to implement tick counter In which sequence of bytes(around KBytes, depends on my counter maximum value, usually equal to block size) allocated to counter for each increment successive bits will be set to 1 to 0 starting from MSB. I will write custom flash driver to take care of counter operations.


Val0: 1111 1111 1111 1111 ....
Val1: 0111 1111 1111 1111 ....
Val2: 0011 1111 1111 1111 ....

Advantages tick counter:

Erase required only when we want to make counter to zero.

But is it possible to program a bit from 1 to 0 without erasing(NAND/NOR), if yes will that effect P/E cycles count?

  • \$\begingroup\$ Why wouldn't you just save the data when the power dies? It'll be easier to get a brown-out IC and put a HUGE capacitor on there instead of worrying when/what/if things will write on time. You just to a "death throw" write to save the state via an interrupt. \$\endgroup\$
    – b degnan
    May 30, 2016 at 12:23
  • \$\begingroup\$ @bdegnan I am just designing software for the product...We don't have enough power to save all the information(we need maintain multiple counters even if we take 4-byte counter it will be some KBs) in flash according to product specifications... \$\endgroup\$ May 31, 2016 at 6:36
  • \$\begingroup\$ FLASH has a pretty high power cost for erasing banks, and what you are describing is generally considered to be poor practice. You basically just write when your required it. The bank erase is a fixed time (generally), so you want something with a single bank. \$\endgroup\$
    – b degnan
    May 31, 2016 at 9:43

2 Answers 2


Rethink your choice of component selection and design in a FRAM chip instead. These support much better performance than Flash because there are no long operational delays on writes and erases. FRAM chips also have endurance capabilities that far out pace those of Flash or EEPROM.

The FRAM chips that I use also support byte by byte data changing as well. This allows for the design of stored block type data in the FRAM chip to be buffered in RAM and then only needing to update specific bytes that have changed as opposed to whole blocks like in Flash. This performance improvement alone can make the serial nature of a SPI or I2C interfaced FRAM chip not bog down an application.

  • \$\begingroup\$ Another option is MRAM (I have used both and they each have their pros and cons). \$\endgroup\$ May 30, 2016 at 10:27
  • \$\begingroup\$ I am just designing software for the product... we should use either NOR or NAND flash for storing data through power cycles... \$\endgroup\$ May 31, 2016 at 6:39
  • \$\begingroup\$ Why should you limit the design to crappy technology when a much better technology exists for the problem you site. Don't be an ostrich and hide your head in a hole in the sand. \$\endgroup\$ May 31, 2016 at 6:43
  • \$\begingroup\$ Hardware team considering that option(Using MRAM) also but that will be last option....And this is the requirement of hardware test software and product software don't have any such issues with current hardware design.... as of now we are looking for turn around using existing resources... as we have plenty of memory (NOR-128MB, NAND-1Gb) I want to know feasibility of tick counter algorithm... \$\endgroup\$ May 31, 2016 at 7:04
  • \$\begingroup\$ Please let me know whether It is possible or not to do program operation(setting bits to 0) with out erase operation? and will the program operation(setting bits to 0) affects the NOR/NAND flash lifetime/PE-erase cycles count...? \$\endgroup\$ May 31, 2016 at 7:04

Erasing a flash segment sets all bits to one.
Programming flash sets some bits to zero.

There are no other ways to change values in flash.

Please note that flash typcially has a limit on the number of programming operations that can be done between two erase operations, and that there often is a minimum word size for programming, so it might not be possible to use, e.g., a 32-bit word to count 32 steps.

  • \$\begingroup\$ How many times a block can be programmed (sets bits to zero) between two erases.... I am thinking of using entire block(NOR flash usual block size - 128Kb) for one counter using tick counter algorithm(as I mentioned in my question)... In that case we can count up to 1 million steps... but that many programming operations allowed between two erases... and will programming(sets bits to zero) will effect flash life time/PE-cycles count/wearout limit? \$\endgroup\$ May 31, 2016 at 6:43
  • \$\begingroup\$ Look into the datasheet. \$\endgroup\$
    – CL.
    May 31, 2016 at 6:46
  • \$\begingroup\$ I couldn't see any information regarding such limit... NOR flash part number "JS28F00AM29EWHA"... datasheet link JS28F00AM29EWHA \$\endgroup\$ May 31, 2016 at 6:50

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