I have this simple code which doesn't behave as it should and can't figure out why.

entity test is
port (D0        : in  std_logic;
        output      : out unsigned(6 downto 0));
end test;

architecture Behavioral of test is
    signal clk_Cent_i : unsigned(6 downto 0);

    gen_clk : process (D0)
    if  D0 = '1' then
    clk_Cent_i<=clk_Cent_i + "1";
    end if;
    end process gen_clk;
output<= clk_Cent_i; 
end Behavioral;

I want by pressing a button to increment a counter and show the counters' number to 7 leds.


If you want to count individual presses, you need to react on signal edges. So, instead of

if  D0 = '1' then

you need to write

if(rising_edge(D0)) then

Warning: this will only work if D0 is correctly debounced, i.e. a single rising edge is produced on each press.

  • 2
    \$\begingroup\$ This will make D0 a clock signal. The switch will likely fail the timings. Better to set up an FSM to monitor the state of the switch on each clock edge. \$\endgroup\$ – user110971 May 30 '16 at 18:17

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