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I'm using a dual digital pot IC controlled with an SPI interface. Each pot goes to a different op amp on the pcb to calibrate two different voltages. Since both pots are in the same package, how big a deal is it if the pots are far from the op amp feedback loops? Typically, the amp resistors should be as close as possible to the amp to reduce noise. The voltages ultimately feed into 12-bit ADCs, so with the resolution being relatively low, can I get away with this as is?

Also, how do the SPI lines affect the DC analog readings if at all? If I keep the digital traces away from the analog values with a ground pour in between will that suffice, or should they be isolated in some other manner?

I'm looking to get the most accurate/stable reading possible. Currently going with a four layer pcb, but may have to reduce it to two.

Thanks

Edit: images added

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  • \$\begingroup\$ You seem to have a good grip on the important issues, like keeping the feedback loops short even if you have to jam the digital pot next to the IC. We need more details if you want answers about the ADCs, such as min/max signal level. \$\endgroup\$ – Sparky256 May 30 '16 at 20:52
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    \$\begingroup\$ Do you have a diagram or a schematic for us to look at? Do you have a board layout yet? Even a good hand sketch will do. \$\endgroup\$ – Sparky256 May 30 '16 at 20:57
  • \$\begingroup\$ if the pot is used for gain control, you probably need to worry less than if its used for a DC offset. I'm not sure there is much specific that anyone can add here - even with schematics and layout - before knowing how your circuit performs and if it needs improvement. \$\endgroup\$ – Sean Houlihane May 30 '16 at 21:05
  • \$\begingroup\$ I kept U17 very close to U4 and U5 is about 600mils away from U4. The upper-half of the pcb is digital and the lower-half is analog, but I have the digital pot in the analog section, which is why I'm concerned about the SPI lines corrupting the analog reading. The O/P of U17 goes across the pcb aways, but there aren't any noisy signals nearby. \$\endgroup\$ – Sunless May 30 '16 at 21:57
  • \$\begingroup\$ The ADCs are 0- 2.4V, so the signals will be attenuated before entering the I/Ps \$\endgroup\$ – Sunless May 30 '16 at 22:05
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How big a deal is it if the pots are far from the op amp feedback loops?

1) A very big issue. But keep the traces together and avoid digital traces. Cross them at a 90 deg angle if you have to. A 5pf to 22pf capacitor across the output and (-) input of the op-amps will stabilize them if you get ringing or parasitic oscillation in the op-amps.

The voltages ultimately feed into 12-bit ADCs, so with the resolution being relatively low, can I get away with this as is?

2) A 12 bit ADC has a resolution of about 4,000:1, so unless some IC is oscillating or you need more decoupling capacitors the ADC should be quiet. Noise levels up to 1/2 LSB are OK and actually prevent the ADC from 'bit locking' due to lack of a signal.

How do the SPI lines affect the DC analog readings if at all?

3) If not isolated by a dedicated ground shield, it is always best to run digital signals at right angles to analog signals. You do NOT want analog and digital lines running close and parallel, as it acts like 2 antennas close together and a good deal of digital noise could be imposed on your analog signals.

4) Pay attention to the basic rules, as you seem to be already doing, and the circuit should work just fine. By that I mean that any 'fine-tuning' or 'trimming' of values will be easy to do to get the best possible performance.

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  • \$\begingroup\$ I usually have the layers stacked as follows: top: power and signals, layer 2: 3.3V, layer 3: gnd and the bottom layer is signal and ground. The top and bottom layers always have copper pours for a ground plane. As long as I run the SPI lines on the bottom layer, and the analogs on the top, should I be fine? I'm using a switcher for power, though I've learned how to isolate it quite well, I'm just concerned with noise from the mcu and the associated digital signals. Thanks for your input. \$\endgroup\$ – Sunless May 31 '16 at 2:01

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