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I made a buck converter, And I tested the circuit under following conditions:

Vi = 32V
R = 6.8 ohm
Fs = 125kHz

I got this result:

enter image description here

I think it's kinda odd that the difference between the theoric output voltage and the experimental one get smaller when the duty cycle increases.

The bigger difference between experimental and theoric voltage happens when the duty cycle is close to 0.5, I think two factors may explain this result:

1) The current ripple has its peak just at a duty cycle of 0.5, bigger currents imply a bigger lost since the Ron of the MOSFET.

2) The second one will be that for a duty cycle under 0.5 most of the time the diode is ON, for a duty cycle bigger than 0.5 the transistor is ON most of the time. Since the power loss in a diode is bigger in the diode this may explain the improvement in the efficiency for a bigger duty cycle

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    \$\begingroup\$ Does your theoretical model include resistors to simulate losses? or does it assume ideal components? \$\endgroup\$ – Tom Carpenter May 31 '16 at 1:25
  • \$\begingroup\$ @TomCarpenter It assumes ideal components \$\endgroup\$ – Luis Ramon Ramirez Rodriguez May 31 '16 at 1:28
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    \$\begingroup\$ In which case your theoretical and practical and bound to be quite different. Probably the most important cause is the fact that an ideal diode has has a forward voltage drop - this will give at least a diode drop difference between simulation and experiment. Also you could try adding a couple of resistors - one for the inductor and one for the transistor (the resistances can be based on nominal values for the components) \$\endgroup\$ – Tom Carpenter May 31 '16 at 1:39
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If your DC/DC doesn't have a synchronous rectifier (i.e. it uses a diode), then your analysis is generally correct.

The major losses in the DC/DC are: 1) Diode -- inversely proportional to duty cycle (VOUT) 2) FET RDSON -- high side switch -- proportional to duty cycle (and load) 2.5) inductor I^R and core losses 3) Switching losses -- proportional to frequency -- constant in your case 4) bias currents etc -- constant

If you keel RLOAD constant, then the FET RDSON losses will increase with VOUT significantly -- as you increase duty cycle, output current will increase, and so will the % time this is flowing in the HS FET. FET losses will increase as duty cycle ^3.

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