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Is there an estimate as to how a common CPU (for example, Intel i7) would improve if all of its logic circuits were reduced to their theoretical minimum, in the sense explained here? By "improve" I mean in metrics such as: size, number of transistors, power consumption, speed.

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closed as too broad by JIm Dearden, PeterJ, Bence Kaulics, old_timer, placeholder Jun 1 '16 at 15:18

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    \$\begingroup\$ What makes you think it isn't done already? Intel isn't a bunch of noobs. \$\endgroup\$ – PlasmaHH Jun 1 '16 at 13:47
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    \$\begingroup\$ Interesting article that looks at this sort of thing: theregister.co.uk/2016/06/01/arm_cortex_a73 \$\endgroup\$ – Peter Smith Jun 1 '16 at 13:48
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    \$\begingroup\$ @EugeneSh.: yeah, I also might claim that it is hand written by 1st sememster liberal arts students \$\endgroup\$ – PlasmaHH Jun 1 '16 at 13:52
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    \$\begingroup\$ @EugeneSh. Yes, one of the most advanced semiconductor companies in the world is using NAND synthesis to make processors. /s \$\endgroup\$ – Brendan Simpson Jun 1 '16 at 14:00
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    \$\begingroup\$ Former Intel employee here, worked in high-speed digital design and serial-IO. Can guarantee you it is not just NAND gates, but are heavily optimized outputs using latest in-house or commercial synthesis (EDA) software. Structured datapath often still done by hand, at least on the critical timing paths. @dwelch There is much more to entering a new market than "bang out a phone or tablet processor" but if you'd like to know more you can read the tomes that have been written on the subject in various industry magazines. \$\endgroup\$ – Joel Wigton Jun 1 '16 at 16:43
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I worked for a decade at a startup doing computerised logic improvement for chip designers; we were eventually bought by Cadence.

We had, among a whole bunch of other tools, a heuristic logic minimiser. It was a fairly simple thing that just pushed "bubbles" (negations) around, and attempted to absorb gates into the slightly more efficient AOI or OAI composite gates. It would then compute a cost function to see if this was a good idea.

What turned out to be far more critical was logic duplication. It seems counterintuitive to add more gates computing the same logic function, but the important thing in ASIC performance is the critical path. The logic path that takes longest to compute determines the speed of the whole chip. Adding additional outputs from a gate slows it down, especially if those outputs are to far-away locations. You could get a noticeable improvement by having two copies of logic to compute f(A,B,C) where one was "fast" and close to where it was needed and another "slow" one to a less-critical destination.

The extreme of this is buffering. A naive logic removal function would take out all your buffers - after all, they're just the identity function - which would save you a lot of area but ruin the speed.

Optimal logic placement is, I think, also NP-complete. It's very similar to subset-sum. Again, this is one of those problems which is easiest to solve in practice by pretending it's linear, throwing it at an LP-solver, and having other bits of program go round tidying up the nonlinearity.

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  • \$\begingroup\$ An additional problem is that even in optimizing for performance one must consider power costs. Yield, i.e., the effect of process variation on the design, must also be considered; a design that provides 20% greater performance for 5% of chips but 50% less .for 90% of chips would typically not be economically practical. (Time to market also limits how much optimization can be done.) \$\endgroup\$ – Paul A. Clayton Jun 1 '16 at 17:46
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The CPU chips that you can buy (for example, Intel i7) are optimized for the maximum speed and lowest power available at the current level of high-volume manufacturing process technology. To be sure they are always working on the feature set, circuit design, device technology, and the manufacturing processes that will help make the next generations of CPU chips even faster and lower power.

Theoretical gates in a college text are quite a different thing from integrating literally billions of transistors on a chip the size of your thumb-nail. The actual transistor-level circuit that goes into a gate is quite different if you compare a simple 7400 quad NAND gate small-scale integration vs. a modern high-end CPU chip.

And approaching the clock-speed limit in traditional Silicon-based semiconductor chips means that increasing performance has shifted to using parallel processing vs. sheer linear-path speed. But there may be other elements that offer speeds beyond what we can get out of silicon.

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