How I imagine synchronous digital networks work: data lines are sampled at rising clock edge, a set of transients occur, system settles, and data lines are sampled again on next rising edge. I would place transients at falling clock edges, that way both Tsu and Th time for sampling are clear. (Somewhat similar to SPI bus behavior.)
What see in a datasheet of a real world device (74595): D flipflops connected in series having a common clock. At the output of the first flipflop, transient on the data line follows rising clock edge with Tpd. The next flipflop needs Th time stable data line after rising edge to operate correctly. Of course it works because Tpd>Th, but it's only a matter of nanoseconds.
My problem with all this is that it's not robust (maybe not the best word). Visualizing stuff on a logic analyzer will be less useful because data lines practically change in sync with clock rising edge. Random errors caused by Th>Tpd are not really visible and go undetected. If I connect another shift register in series from a different technology, which requires longer hold times, the circuit won't work, no matter how slow clock I chose.
Is this the way most commonly synchronous digital circuits are constructed? Only the propagation delay of components make it work? Am I being to idealistic? :)