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How I imagine synchronous digital networks work: data lines are sampled at rising clock edge, a set of transients occur, system settles, and data lines are sampled again on next rising edge. I would place transients at falling clock edges, that way both Tsu and Th time for sampling are clear. (Somewhat similar to SPI bus behavior.)

What see in a datasheet of a real world device (74595): D flipflops connected in series having a common clock. At the output of the first flipflop, transient on the data line follows rising clock edge with Tpd. The next flipflop needs Th time stable data line after rising edge to operate correctly. Of course it works because Tpd>Th, but it's only a matter of nanoseconds.

My problem with all this is that it's not robust (maybe not the best word). Visualizing stuff on a logic analyzer will be less useful because data lines practically change in sync with clock rising edge. Random errors caused by Th>Tpd are not really visible and go undetected. If I connect another shift register in series from a different technology, which requires longer hold times, the circuit won't work, no matter how slow clock I chose.

Is this the way most commonly synchronous digital circuits are constructed? Only the propagation delay of components make it work? Am I being to idealistic? :)

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You are correct in your gut feeling that there is a potential problem. Within a chip, the chip designer chaps have taken care of it. When you connect a chain of let's say 74x595's you can indeed run into trouble, especially with a long chain, a weak driver, and clock wiring that starts at the 'first' chip (the one that receives the data). A 'standard' solution is to feed the clock starting at the last chip.

A better solution is to use a chip like the CD4094 that has a delayed output. It has an extra flipflop, that is clocked on the opposite edge. Using this output to feed the nect SR eliminates all setup/hold problems (but it does reduce the maximum clock frequency).

I think you can achieve the same effect (sort of poor man's implementation of the delayed output) by clocking the even 595's with the plain clock, and the odd 595's with the inverted clock. But I never really worked this out.

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  • \$\begingroup\$ Clocking alternate 595's with opposite clock edges limits one to using 15 bits for each pair of 595's (after every edge where the second 595 is clocked, its first stage will hold the same data as the last stage of the previous one, meaning that the 595's together only hold 15 distinct bits). \$\endgroup\$ – supercat Dec 15 '11 at 22:42
  • \$\begingroup\$ Makes sense, the last stage is more or less used as the delayed stage in a 4094. \$\endgroup\$ – Wouter van Ooijen Dec 16 '11 at 8:23
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    \$\begingroup\$ It's nice that the 4094 has such a delayed stage. I wonder why latches which sample on one edge and change on the other aren't more common? If a chip can internally turn rising and falling edges into pulses which are sufficient to operate a transparent latch, but which are shorter than the minimum and maximum allowable clock-pulse widths, the only extra logic required versus a single-edge clock would be in the clock-conditioning circuitry. \$\endgroup\$ – supercat Dec 16 '11 at 17:33
  • \$\begingroup\$ I think that is because your assumption does not hold. A register is not a latch with clock-conditioning, it is two transparent latches , one being driven by the inverted clock. Your idea would require two such regsiters (or maybe three latches). I think the usefullness of such a device did not blance the added circuitry and worse maximum speed. \$\endgroup\$ – Wouter van Ooijen Dec 16 '11 at 20:19
  • \$\begingroup\$ There are a number of ways registers can be implemented. A common register implementation is essentially a master/slave flip flop, where the slave is designed to start passing data at about the same time as the master stops passing it. Many devices, have historically, however, handled latching by using transparent latches along with two non-overlapping clock signals. Typically the non-overlapping clocks were 180 degrees out of phase, but there's no reason they'd have to be. This approach meant that in those parts of the device which didn't have to run at the fastest possible speed... \$\endgroup\$ – supercat Dec 16 '11 at 20:46
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Yes, but what the schematic doesn't show is that the IC designer has included a small delay on the data line. In a normal situation, the data would be going through some logic gates and doing "real work" before being sampled

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  • \$\begingroup\$ It's entirely reasonable for data to not go through logic gates; but if that violates hold time, you need to add explicit delays. \$\endgroup\$ – Jason S Dec 16 '11 at 16:57
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My problem with all this is that it's not robust (maybe not the best word). Visualizing stuff on a logic analyzer will be less useful because data lines practically change in sync with clock rising edge. Random errors caused by Th>Tpd are not really visible and go undetected. If I connect another shift register in series from a different technology, which requires longer hold times, the circuit won't work, no matter how slow clock I chose.

You bring up two issues. Let's call the two synchronous circuits A and B, where A feeds into B, and both share the same clock

  1. Circuit won't work if total Tpd(A) < Th(B) where Tpd is the combinational delay of the clock. Is this true? Absolutely! You're the circuit designer and it's your final responsibility to make sure the circuit works. In reality, it's not usually a source of worry; even if you feed one register output right into another's input, the design margin of the chip's specs is high. For a NXP 74HC595, for example, typical propagation delay at 4.5V supply is 19ns, required hold time is 3nsec, and typical hold time is -2nsec -- no problem there. For a TI SN74LV595A at 5V, typical propagation delay is 4.5nsec, minimum propagation delay is 1nsec, required hold time is 2nsec. Could this be a problem if the propagation delay and hold times are at their worst case? Absolutely. Could it be a problem if you cascade a SN74LV595A into an NXP74HC595? Absolutely. In those cases you may need to add combinational elements (buffers) with enough delay to make sure the hold time is met.

  2. "Visualizing stuff on a logic analyzer will be less useful because data lines practically change in sync with clock rising edge." True. Take a tip from SPI buses, and set the logic analyzer so that it samples the data on the clock falling edge. SPI's rules are simple: you update outputs on one edge, and you sample inputs on the other.

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