It seems bclk can only sample the pulse of adat once (at the second rising edge of bclk), which causes output metastability on bq1_dat. How can bq1_dat be sampled "high" on the next active clock edge?
In addition to my question, I'd like to add what I think for a signal to go through safely to another clock domain (suppose 2-FF is enough to satisfy MTBF requirement). Please correct me if any mistakes.
The original figure came from Lecture notes for EE108A, Lecture 13: Metastability and Synchronization Failure (ow When Good Flip-Flops go Bad) by W. J. Dally.