I am currently working on a design which includes the AIS3624DQ accelerometer from ST. In the datasheet, it says (section 4, page 17):

"Power supply decoupling capacitors (100 nF ceramic, 10 μF aluminum) should be placed as near as possible to the pin 14 of the device (common design practice)."

Can I replace the 10μF aluminum (due to its large size) with a tantalum capacitor instead?

  • \$\begingroup\$ What current rating is the power supply? See electronics.stackexchange.com/questions/99320/… \$\endgroup\$
    – user16324
    Commented Jun 2, 2016 at 10:51
  • \$\begingroup\$ I couldn't find those words in the data sheet - maybe a link to that DS would help. \$\endgroup\$
    – Andy aka
    Commented Jun 2, 2016 at 10:56
  • \$\begingroup\$ @Brian Drummond, we are on 3.3V \$\endgroup\$
    – chris
    Commented Jun 2, 2016 at 10:57
  • \$\begingroup\$ @Andyaka , here page 17: st.com/content/ccc/resource/technical/document/datasheet/group1/… \$\endgroup\$
    – chris
    Commented Jun 2, 2016 at 11:02
  • 12
    \$\begingroup\$ 3.3V is not a current rating. \$\endgroup\$
    – user16324
    Commented Jun 2, 2016 at 11:25

4 Answers 4


You can replace the aluminum electrolytic with a tantalum, but using neither is a much better choice.

Nowadays, ceramics can easily cover the 10 µF at 10s of volts range. There is no point using either a electrolytic or tantalum. You also don't need a separate 100 nF (that value is so 1980s anyway) capacitor if you use a ceramic for the larger value.

Think about what is going on here and what the datasheet is trying to say. These devices are notorious for being quite sensitive to power supply noise. I've actually seen a similar part amplify power ripple from the power supply to the output. The datasheet therefore wants you to put a "large" amount of capacitance on the power line to the device. That's where the 10 µF came from. Back when this datasheet was written, or whoever wrote it stopped keeping up with developments, 10 µF was a unreasonably large request for any capacitor technology that was good at high frequencies. So they suggest a electrolytic for the 10 µF "bulk" capacitance, but to then place a 100 nF ceramic across that. That ceramic will have lower impedance at high frequencies than the electrolytic, despite the fact that it has 100 time less capacitance.

Even in the last 15-20 years or so, that 100 nF could have been 1 µF without being burdensome. The common value of 100 nF comes from the ancient thru-hole days. That was the largest size cheap ceramic capacitor that still worked like a capacitor at the high frequencies required by digital chips. Look at computer boards from the 1970s and you will see a 100 nF disk capacitor next to every one of the digital ICs.

Unfortunately, using 100 nF for high frequency bypass has become a legend on its own. However, the 1 µF multi-layer ceramic capacitors of today are cheap and actually have better characteristics than the old leaded 100 nF caps of the Pleistocene. Take a look at a impedance versus frequency graph of a family of ceramic caps, and you'll see the 1 µF has lower impedance just about everywhere compared to the 100 nF. There may be a small dip in the 100 nF near its resonant point where it has lower impedance than the 1 µF, but that will be small and not very relevant.

So, the answer to your question is to use a single 10 µF ceramic. Make sure whatever you use still is actually 10 µF or more at the power voltage you are using. Some types of ceramics go down in capacitance with applied voltage. Actually today you can use a 15 or 20 µF ceramic and have better characteristics across the board compared to the 100 nF ceramic and 10 µF electrolytic recommended by the datasheet.

  • 2
    \$\begingroup\$ I wonder if 2x 10uF ceramic in parallel would be the best way to go even? And yes, 100nF comes from the pre-MLCC days -- you can get 10+uF ceramics cheaply nowadays in both SMT and THT packaging. \$\endgroup\$ Commented Jun 2, 2016 at 11:32
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    \$\begingroup\$ @Three: More capacitance shouldn't hurt. For a sensitive chip like this, I'd probably use two ferrite chip inductors in series, each followed by a 20 uF ceramic cap to ground. If the power supply is a switcher or otherwise has significant noise on it, I'd use a little higher supply with a local LDO just for this part. The ferrite and caps described above would go on the input of the LDO, then a single 1 uF on the output of the LDO and power input of the chip should be fine. All three (LDO, 1 uF cap, chip) should be physically close together. \$\endgroup\$ Commented Jun 2, 2016 at 11:37
  • 3
    \$\begingroup\$ But why do even modern datasheets recommend the 100nF? My professor at university (HF Design) even recommends values in the pF Range. \$\endgroup\$
    – Michael
    Commented Jun 2, 2016 at 17:44
  • 3
    \$\begingroup\$ @Mich: For really high frequencies like 100 MHz or more, even some ceramic capacitors don't act like capacitors anymore. I once used 100 pF bypass caps in a RF system, and then specified a particular model, because other caps had higher impedance at the RF frequency. \$\endgroup\$ Commented Jun 2, 2016 at 18:07
  • 2
    \$\begingroup\$ @Bip: Small packages help because they have less parasitic series inductance. Be careful generalizing size though. The technology and materials matter. \$\endgroup\$ Commented Jun 3, 2016 at 11:17

Contrary to Olin Lathrop's answer, ceramic capacitors are not the solution to all board-level bypass problems. It is even possible for the choice of only ceramic capacitors to be detrimental to the performance of a design.

An important fact about certain ceramic dielectric formulations is that they exhibit piezoelectric behavior: they can convert mechanical energy to/from electrical energy. For an accelerometer, this microphonic behavior can couple 100s of Hz vibration into the power supply of the device. This vibration is exactly in the frequency band of interest because it's what the accelerometer is measuring, meaning that it can't be filtered out digitally.

Ceramic capacitors also have a characteristic loss of capacitance with applied DC bias. For instance, the capacitance versus DC bias curve of the Murata GRM188R61A106KAAL# device is:

Murata GRM188R61A106KAAL capacitance versus DC bias

From the interactive chart, at the typical 3.3V operating input, this specific capacitor only has an effective capacitance of 5.337uF, a loss of almost 50% of the rated capacitance at under half of the rated DC bias. While the bulk capacitance of this application does not require a specific value, this can be a "gotcha" for applications with a minimum capacitance requirement.

Additionally, the ESR of aluminum electrolytic and tantalum capacitors can be advantageous. Because it makes the capacitor lossy, it will dampen oscillations and can help limit the peaks of transients. Linear Technology has an application note describing the hazards of using only ceramic capacitors on hot-plug power supply inputs. Additionally, some power supplies have output bypass capacitance ESR requirements, as discussed in this TI application note. To use very-low-ESR ceramic capacitors actually requires defeating their low ESR by installing a 10s of milliohm resistor in series with the capacitor.

  • \$\begingroup\$ Your graph is absolutely horrible! I'm looking to bypass an op amp at +/- 15V. A typical by passer is 100nF. Is this bias derating common to all ceramics, or just your small SMT type? Do we just have to use 100V rated ceramics for old level voltages instead? \$\endgroup\$
    – Paul Uszak
    Commented Jan 1, 2017 at 14:29
  • 1
    \$\begingroup\$ @Paul: This answer is misleading in that it picks a particularly extreme part and implies it serves as a general example. Capacitance decrease with voltage certainly exists, but there are also many cheaply available parts that react much better than what is shown. This is not common to all ceramics or SMD capacitors. It is a function of the ceramic. For high-volume non-exact use, like bypassing, it can be worth the little extra savings to use cheap ceramics. Better ceramics aren't that much more money, and you can also compensate by using a higher starting capacitance in some cases. \$\endgroup\$ Commented Apr 29, 2017 at 13:32

The aluminium capacitor appears to be a bulk bypass device.

Tantalums typically have lower ESR than aluminium devices, but that should not be of importance here as the ceramic device is going to be low ESR anyway.

So you should be fine using a tantalum device in place of the aluminium electrolytic.

Make sure you use a device rated for at least 2Vcc.


There are some good answers already (just use MLCC), but I would add that for high-frequency decoupling you should use closely coupled (ie. no core between) layers of supply voltage and ground. Make their overlapping area as large as convenient, and place multiple vias as close to the IC supply/ground pins as possible. This is the best way to get really high-frequency decoupling. Then place your MLCC capacitors as close to those vias as reasonably possible. Avoid multiple capacitor values and rather use with multiple identical capacitors if one is not enough. The risk of using for example 10n, 100n, 1u in parallel is resonant impedance peaks.

This above will give you the lowest total impedance for your decoupling.

Also, you should avoid ferrite beads for digital ICs, but this is of course implied in the above.


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