If a microcontroller has 16 bit address space from 0000H to FFFFH, will the RAM, I/O registers, memory mapped I/O and ROM(Flash/EEPROM) share the same address space linearly, or will there be a separate address space for ROM alone(like another 0000H to 1FFFH), or is it manufacturer dependent?

I guess I read lot of documents and confused myself into this. Please help.

  • 3
    \$\begingroup\$ It's best if you select a specific device, then read the datasheet, then ask here if it's not clear. \$\endgroup\$ Jun 2, 2016 at 13:47
  • \$\begingroup\$ Typically there will be different non contiguous spaces because of address decoding limitations and device size discrepancies \$\endgroup\$ Jun 2, 2016 at 13:49
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    \$\begingroup\$ This depends entirely on the device. For PIC, yes; ARM, no. And so on. \$\endgroup\$
    – pjc50
    Jun 2, 2016 at 13:50
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    \$\begingroup\$ I would question the existence of a typical microcontroller \$\endgroup\$
    – PlasmaHH
    Jun 2, 2016 at 13:52
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    \$\begingroup\$ @ClaudioAviChami - having a common address space does not require having a contiguous one. Essentially, what it means is that some of the same software-level access methods (at minimum, a read) can be used. \$\endgroup\$ Jun 2, 2016 at 14:35

2 Answers 2


That is in fact the key difference between "von Neumann" and "Harvard" architectures. The first uses a single address space for everything, while the latter has separate address spaces for instructions (usually ROM) and data (usually RAM).

You can get microcontrollers with either architecture. Some implement a hybrid of the two.

  • \$\begingroup\$ That was a striking point! But how exactly would be a hybrid of the the two? Little more insight please..? \$\endgroup\$
    – stenvar
    Jun 2, 2016 at 14:03
  • \$\begingroup\$ Some architectures (notably 8080 and derivatives) use separate address spaces for I/O \$\endgroup\$ Jun 2, 2016 at 14:08
  • \$\begingroup\$ For example, the 8051 is a Harvard machine, but it has instructions that allow data to be moved from instruction space. Also, if you connect external memory to it, it's easy to"fold" the address spaces on top of each other, either partially or fully. \$\endgroup\$
    – Dave Tweed
    Jun 2, 2016 at 14:10
  • \$\begingroup\$ ARM Cortex-M parts have a single address space, but as a speed optimization distinct implementation mechanisms and internal data paths for the different types of storage. The same could be argued effectively be true for any modern large system with distinct instruction and data caches. \$\endgroup\$ Jun 2, 2016 at 14:37
  • \$\begingroup\$ An example of a 'hybrid' Harvard architecture is PIC24. It has a "PSV" feature (Program Space Visibility) which allows program memory to be partially mapped in to the upper 32K region of SRAM. It can then be used as a ROM. The SRAM bus is only 16-bit wide though, but given the typical RAM size of these devices that poses not a problem. \$\endgroup\$
    – Hans
    Jun 2, 2016 at 14:51

Dave has already mentioned the differences between Harvard and von Neumann architectures.

An example of a von Neumann architecture, where there is just one address space for RAM, Flash, I/O and EEPROM, is the HCS08 family from Freescale. Here is the memory map of one of its microcontrollers that has 128K of Flash and 4K of RAM:

enter image description here

Note in this figure, memory address 0 is at the top. It is also not to scale; the address 0x8000 (32K boundary) should be exactly in the middle.

This microcontroller has a direct page (sometimes called page 0), i.e. 256 addresses which can be accessed with just an 8-bit address (which reduces the size of the instruction by a byte). The first 128 locations, 0x0000 to 0x007F are used to map I/O registers. This is followed by the 5K of RAM, from address 0x0080 to 0x17FF. By doing this, the first 128 bytes of RAM are also located in page 0. This is followed 256 additional addressed reserved for additional I/O registers at 0x1800 to 0x18FF, then more RAM, then the first segment of Flash, then 2K of EEPROM.

Then additional pages of Flash. Note they have page numbers too (PPAGE). Remember I said this microcontroller has 128K of Flash? How do you fit that into 64K of address space? By using paged addressing. There is a "paging window" at 0x8000 to 0xBFFF (16K) where one of eight 16K pages of Flash (128K total) can be mapped. Which one is controlled by a paging register. When the compiler is generating jumps or subroutine calls, it knows to update the paging register as needed.

Some of the pages can also be addressed directly (PPAGES 0, 1, and 3) without using the paging register. This is needed for things like interrupt handlers, which may occur at any time. Common subroutines, like the C library, are also good candidates for these pages.

Not shown are the reset and interrupt vectors, which start and the top of memory (0xFFFF) and go down.

Pure Harvard architecture machines have much simpler schemes, there is one address space for Flash starting at 0x0000, another for RAM starting also at 0x0000 and still another for I/O ports starting at 0x0000 (sometimes RAM and I/O are put together in the same space, known as memory-mapped I/O). If I/O ports are used, they acre accessed via special instructions such as IN and OUT.

Because they are separate spaces, they can have different widths. The PIC16 microcontroller from Microchip for example, has a 14-bit instruction width and 8 bit RAM and I/O busses.

What's the advantage of each? Well with a Harvard architecture, you can have 64K of program space, 64K of RAM space, and 64K of I/O space, all using 16-bit addresses. So it's good for 8 and 16-bit microcontrollers. Because the program is in Flash, it can't be modified.

With von Neumann architectures, you can run programs out of either Flash (or ROM) and RAM. This is how PC's work: when they first start up, they boot up using a BIOS (Basic Input/Output System) ROM, which reads the OS off of a hard drive and loads it into RAM. From then on, programs execute out of RAM.

There are also "modified Harvard architecture" processors, which allow part of the instruction space to be viewed as if it were "read-only" RAM. This is usually done using a paging window similar to the one in the HCS08 diagram earlier. In the PIC24, this feature is called Program Space Visibility (PSV).

  • \$\begingroup\$ Though I feel it to be a little difficult to understand the address spacing described in the first part, it answered most of my doubts surrounding this topic. \$\endgroup\$
    – stenvar
    Jun 2, 2016 at 17:28

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