I am working with Altium.
What verification do you particularly do when going from schematic to layout in terms of electronic and in terms of capture ?
With Altium, it's a nicely integrated environment with very tight coupling between schematic and layout aspects. Altium has a concept of component links which you can use to verify that every component on the PCB is linked to something on the PCB. Additionally, as Bence mentioned in a comment above, there are DRC and ERC rules matrices you can use to verify your design.
ERC is used in the schematic editor and can detect floating nets, unconnected ports, multiple net-name violations, etc. Altium has the concept of "compiling" your design -- this should be error and warning free, but at the least, you should understand why any errors/warnings are occurring and sign off on them appropriately. The most important error (IMHO) that ERC should catch for you are single-pin or floating nets -- embarassing when a design doesn't work because you typo'd a net-name and they actually aren't connected to each other.
DRC is used in the PCB editor and is for physical rules checks -- floating nets, close clearances, soldermask slivers, high-speed routing, annular ring etc. You should look at your fab's requirements and input them as a default rule set in Altium. This is more applicable to the physical PCB during/after layout.
(More of a tip): I personally don't use Altium's ability to define inputs/outputs/bidirectional/etc pin types on components -- it's always caused more trouble for me than it helps. As a design principle (again, IMO), components with serial links (UARTs, PCIe, etc.) should have visual arrows/indicators on their schematic symbols Tx/Rx so you can verify you don't have a connectivity problem. Some manufacturers name their outputs TxD/Tx, others try to "help" you and name their inputs TxD/Tx, so you connect the wires there. Altium will not automatically catch this for you unless you are defining pins as inputs/outputs, in which case then the ERC can let you know you've goofed up.
As a matter of principle/process, the answer to this question depends on your corporate environment, IMO. In an environment where the schematic designer is also the layout engineer, the transition is much easier, though there should still be a review stage where your peers help you sign off on the schematic, within reason. Pin-swaps and similar are common during layout, and the schematic should be re-verified at the completion of layout as well.
In an environment where you are handing off to layout, it's imperative that you define layout requirements, potentially by writing a guide. Recall that in Altium, you can use net classes and parameter flags to define what nets are controlled impedance, etc. You can also leave temporary notes on the schematic that call out things the designer may not be aware of, such as the need to place certain decoupling caps across certain pins.