5
\$\begingroup\$

I'm confused about metastability. I know that metastability is the condition wherein the output of a flip flop becomes unpredictable (either high or low) for some "duration of time"... Okay, from this definition, it states that metastability will not go on forever, right? Does this mean that after this period, the output of the flop will eventually go to the correct value? Or does it go into an unpredictable value depending on which value has been generated after the metastable period???

Take note, I'm asking here what happens AFTER the metastable period, NOT during the metastable period.


@Neil_UK,

So in the image below, the 2nd flop will not always samples a high value. Am I right?

If the first flop becomes metastable then after sometime the metastability has decayed, its value may settle randomly at either logic 0 or logic 1. Is this correct?... I'm asking this because the author says that it samples the value as high. I don't know how did it sample a high value. Is it just by chance that the output of the first flop settles at logic 1?

If the first flop did not go out from metastable state within one bclk period, then the second flop will also become metastable... and this could also happen when another stage of flop is connected... Is this what you mean that there is no guarantee that a Synchronizer will 'absolutely' give the correct intended output?

I'm reading some stuffs about metastability and synchronizers. I'm confused on the explanation of some of the authors, like this one. I'm reading this article, http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf on page 9.

Synchronizer

\$\endgroup\$
  • \$\begingroup\$ If your circuit survives the metastability, then yes it will settle. \$\endgroup\$ – Jasen Jun 3 '16 at 4:34
  • \$\begingroup\$ There is some threshold where a signal above is a "1" and a signal below is a "0", when you're dancing around the threshold (especially during a clock edge), you get metastability, once you're far enough from that threshold and the clock has finished transitioning it's back to normal operations \$\endgroup\$ – Sam Jun 3 '16 at 4:50
  • \$\begingroup\$ Mr Cummings is very confusing there, how his paper was voted best I don't know. You are right. There is no reason that an output that is still metastable should be seen as either a 0 or a 1. His fig 3 should either show metastability ending on the first flop with the output going solidly to 0 or 1, OR still metastable when the second latch clocks, and comment that it could be received as 0 or 1. Diagrams like this are clearer where adat has a pulse that last several clock cycles, it's confusing to have setup/hold violations on several edges. \$\endgroup\$ – Neil_UK Jun 6 '16 at 8:40
  • \$\begingroup\$ I'm glad you're getting there, and it's very disappointing to see confusing diagrams in papers like the one you've quoted in the public domain. He has not quite defined why metastability is a problem properly either. It's when a mis-latched signal can be taken as different states by different parts of the receiving system, either at different times, or in different places, that the inconsistency between these states is important. What a synchroniser does is get to a stable unambiguous level. I haven't read his paper in detail, but I haven't yet spotted the statisitical nature of the 'fix'. \$\endgroup\$ – Neil_UK Jun 6 '16 at 8:45
  • \$\begingroup\$ If there is a correct value then the circuit doesn't become metastable in the first place. \$\endgroup\$ – immibis Jul 9 '17 at 10:54
7
\$\begingroup\$

You have some misconceptions about metastability

1) You talk about AFTER the metastability period.

The whole point is that, although you can scope the waveform after the event, and figure out when things ended, the circuit, trying to do the decision job, at the time, has no way to 'observe' the whole waveform, it cannot look into the future. Circuits that try to overcome metastability by determining when it has ended, suffer from metastability in the 'has it ended' decision block.

2) You talk about the 'desired' result being '1'.

Metastability only occurs when the correct result could be 1, could be 0, dosen't matter which, but has to be solidly one or the other.

For instance, an asynchronous interrupt arrives at a processor with a different clock to the one generating the interrupt. It doesn't matter whether the interrupt processes this cycle, or next cycle, as long as it does one or the other.

If it is important that the interrupt processes this cycle, then your interrupt has to meet the setup for the processor interrupt with respect to its clock. If it doesn't, you have a system design problem, not a metastability problem.

Metastability resolves itself exponentially. If the likelyhood of still being metastable after 1nS is (say) 1e-6, then after 2nS it will be 1e-12, and after 10nS it will be 1e-60. You will notice that this last probability is still not zero, but you are unlikely to see it in your lieftime, or indeed the age of the universe. If you did, you would be hard-pushed to repeat it!

So, if you wait long enough, metastability becomes too small a problem to be a practical problem. You MUST allow enough latency for that decision to be made.

But you may not wan to run your system clock slow enough. Pipelining! Just like you do with slow multipliers or execution control units. Spread the operation out over several serial execution units and run your clock quickly. The process 'wait' is just a D flop. Use a string of two or more D flops until you have waited the requisite time to reduce the effect of metastability to 'unlikely in the age of the universe'.

There are two ways to send a d-flop metastable. The first is by violating the setup/hold input timing requirements. The second is by violating the logic levels. The first will typically happen when an event generated in a different clock domain arrives at a clocked input, the first flip flop of a synchroniser. As the clock domains are different, here is no guarrantee that timing requirements will be met, and a fast data edge can occur at the same time as the clock signal. The second will typically happen between the first and second flops in a synchrnoiser, if the first flop has been sent metastable, and is generating an intermediate logic level out. This may be read as 0 or 1 by the following flop, or may send that metastable as well.

Think of a synchroniser as being asked to make a decision of whether the 0 to 1 data transition occurred first, or the clock. If the clock, the output is 0. If the data transition, the output is 1. A d-flop that is in the process of latching is an amplifier, with positive feedback. As an amplifier, made from real transistors, it has a bandwidth. You can see what happens to the setup and hold times in a datasheet for cmos d-flops as the supply voltage changes, and as a result their bandwidth changes. Larger bandwidth can resolve smaller setup and hold times. But, as the data edge approaches, and then crosses through the timing of the clock edge, the time difference becomes infinitessimal, and so the bandwidth required to make the decision becomes infinite. You cannot have an infinite bandwidth amplifier, and a finite bandwidth amplifier cannot guarantee to make the decision in any finite time. Metastability. But the longer you wait, the exponentially more likely it is to have made a decision. But not guaranteed.

\$\endgroup\$
  • \$\begingroup\$ Thanks for the reply, Neil. Let's say the clock period of the flop is 10ns. Then let's say at the rising edge of the clock, D input also rises causing the flop to become metastable. During the metastability period, the Q output of the flop will oscillate making the output unstable to either 1 or 0... After waiting for 7ns, the Q output becomes very less metastable making the Q output to have a very high probability of giving the correct value, which is 1. Is this what you mean? \$\endgroup\$ – ReubenMijares Jun 3 '16 at 8:10
  • 1
    \$\begingroup\$ @ReubenMijares NO. If the output of the flop becomes metastable, that means the input setup time was violated, which means there is no 'correct' output value. The output will not oscillate, but will go to an intermediate value between logic 0 and logic 1, which following logic inputs cannot guarantee to read as either 0 or 1, that is why it causes problems, two different following circuits might read it as different things. Like a pencil balanced on its point, once it starts to lean either way, it falls very quickly. Each time period, it is likely to become 1 or 0, but may not. \$\endgroup\$ – Neil_UK Jun 3 '16 at 8:18
  • \$\begingroup\$ If the output goes to an intermediate value (neither 0 nor 1), then how does a Synchronizer circuit (2 cascaded flops) guarantees that it outputs the correct intended value from the master circuit?... I mean, if the first flop of the Synchronizer becomes metastable, then the second flop of the Synchronizer will have different readings and it will propagate this reading up to the output of the Synchronizer, making the output unreliable to provide the correct intended value of the transmitting circuit (master circuit). I'm looking at how Synchronizer (2 flops) resolves the metastability issue \$\endgroup\$ – ReubenMijares Jun 3 '16 at 9:28
  • \$\begingroup\$ A synchroniser (that is, a pipeline of further d-flops) does not guarrantee the output is correct, it only reduces the likelyhood that it's wrong. The metastibilty issue is not resolved by making it never happen, it is resolved by making it so unlikely that you will never see it in practice. You have a higher chance of being struck by a meteorite than seeing a metastable-hard synchroniser remain metastable at the required decision time if it has been well designed. But neither event is impossible. \$\endgroup\$ – Neil_UK Jun 3 '16 at 12:55
  • \$\begingroup\$ @ReubenMijares I've added a couple of paragraphs to my answer. Don't know whether these will help. \$\endgroup\$ – Neil_UK Jun 3 '16 at 13:29
3
\$\begingroup\$

If the flip flop is sampling an input signal -- e.g. a D flip-flop and the 'D' input is changing at the same time as the clock, then the correct slew is indeterminate -- there is no 'correct value' -- either value is correct.

Now -- in practice, the output will settle to a value; because the metastable flop-flop is a high gain circuit starting from an unstable equilibrium point, the settling is achieved exponentially -- as the signal deviates from the balance point, it changes faster and faster. The time to settle to a stable state is best described statistically -- e.g say 90 % of the time it will settle within 2 ns; 99 % within 3 ns; 99.999 % within 5 ns etc.

\$\endgroup\$
  • \$\begingroup\$ Hi jp314. Thanks for your info. Then I think there will still be a problem even after adding Synchronizer flops... Let's say the desired Q value of the designer is 1. If the D input and the CLK becomes 1 at the same time, then metastability can occur. This means that the Q can be either 0 or 1 after the metastability period... If the result is 0 then this will be propagated to the 2nd flip-flop of the Synchronizer, thus the resulting output is still 0 which is incorrect. So no matter how many stages of flip-flops the synchronizer have, the resulting output is still 0. \$\endgroup\$ – ReubenMijares Jun 3 '16 at 4:25
  • \$\begingroup\$ If the D-input transitions 0->1 at the same time as the clock edge, this transition is lost. If D stays high, on the next clock cycle, the correct 1 value will appear on the output. Synchronisation flops are all? about making sure the final output always has a 0 or 1 value soon after the clock edge. \$\endgroup\$ – Sean Houlihane Jun 3 '16 at 15:24
1
\$\begingroup\$

As I remember from an experience executed at my university in 1995, the flip flop does not settle to a known value. Also the duration of the metastability follows a statistical expression and can take a very long time.

Metastability implies that the FF circuit is in a linear operation mode (rather than a saturated operation) where it is kind of stable (=metastable) in between the extreme states. Sufficient noise can then make it go either up or down.

You can compare this to a teeterboard (paradigm). It is stable when either side is down, but you can put it in a metastable state when you carefully balance the teeterboard horizontally. The slightest disturbance will make it go either way. It could stay horizontal for a long time, but it really depends on "noise" like wind, vibrations, bypassers, etc.

With FFs, it is assumed in practice that clocking the same "slower" asynchronous signal in two sequential FFs will avoid metastability. But there is a formula indicating the probability that the FF is still metastable on the n-th clock. How you actually handle it depends how critical the application is. You can clock the signal many times until you reach an acceptable level of failure which is statistically inevitable but can be extremely low.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.